초록 ▼

A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so tha

A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

대표청구항 ▼

[ We claim:] [11.] A circuit for accessing data in a memory array, the circuit comprising:means for sensing a bit in the memory array;a plurality of stages including a first stage and a second stage;a first interconnect coupled to the first stage configured to receive a first data signal that is dep

[ We claim:] [11.] A circuit for accessing data in a memory array, the circuit comprising:means for sensing a bit in the memory array;a plurality of stages including a first stage and a second stage;a first interconnect coupled to the first stage configured to receive a first data signal that is dependent on the logic level of the bit;a second interconnect configured to couple the first stage to the second stage;an output line coupled to the second stage;means for generating a first clock signal, the first clock signal having a first pulse;means for generating a second clock signal, the second clock signal having a second pulse, wherein the second pulse causes the first stage to generate on the second interconnect a second data signal as a function of the first data signal; andmeans for generating a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse, wherein the third pulse causes the second stage to generate onto the output line an output signal that is dependent on the second data signal;wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.