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Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/60
출원번호 US-0058460 (1998-04-10)
발명자 / 주소
  • Sharangpani Harshvardhan P.
  • Hammond Gary N.
  • Mulder Hans J.
  • Arora Judge K.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Faatz
인용정보 피인용 횟수 : 46  인용 특허 : 4

초록

A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, an

대표청구항

[ We claim:] [1.] A processor comprising:branch prediction logic to identify whether resolution of a condition corresponding to a first conditional program flow control instruction is unlikely to be predicted accurately, the first conditional program flow control instruction indicating a first code

이 특허에 인용된 특허 (4)

  1. Dietz Carl D. (Frisco TX) Golla Robert T. (Plano TX) Olson Christopher H. (Austin TX), Method and system for minimizing branch misprediction penalties within a processor.
  2. Sharangpani Harshvardhan P. ; Hammond Gary N. ; Mulder Hans J. ; Arora Judge K., Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch i.
  3. Emma Philip G. (Danbury CT) Knight Joshua W. (Mohegan Lake NY) Pomerene James H. (Chappaqua NY) Puzak Thomas R. (Ridgefield CT), Simultaneous prediction of multiple branches for superscalar processing.
  4. Kimura Kozo (Osaka JPX) Yoshioka Kosuki (Katano JPX) Kiyohara Tokuzo (Osaka JPX), Speculative execution processor.

이 특허를 인용한 특허 (46)

  1. Van Hook, Timothy J.; Hsu, Peter Yan-Tek; Huffman, William A.; Moreton, Henry P.; Killian, Earl A., Alignment and ordering of vector elements for single instruction multiple data processing.
  2. van Hook,Timothy J.; Hsu,Peter; Huffman,William A.; Moreton,Henry P.; Killian,Earl A., Alignment and ordering of vector elements for single instruction multiple data processing.
  3. Dieffenderfer,James N.; Doing,Richard W.; Stempel,Brian M.; Testa,Steven R.; Tsuchiya,Kenichi, Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor.
  4. Dieffenderfer, James N.; Doing, Richard W.; Stempel, Brian M.; Testa, Steven R.; Tsuchiya, Kenichi, Apparatus and method for decreasing the latency between instruction cache and a pipeline processor.
  5. Ekner, Hartvig W. J.; Stribaek, Morten; Laursen, Soeren R. F., Binary polynomial multiplier.
  6. Puzak, Thomas R.; Hartstein, Allan M.; Charney, Mark; Prener, Daniel A.; Oden, Peter H.; Srinivasan, Vijayalakshmi, Branch history guided instruction/data prefetching.
  7. Kuo, Chien Cheng, Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths.
  8. Fontaine,Lawrence Richard; Kuslak,John Steven; Lucas,Gary John; Pelarski,Michael David, Condition indicator for use by a conditional branch instruction.
  9. Stribaek, Morten; Paillier, Pascal, Extended precision accumulator.
  10. Stribaek,Morten; Paillier,Pascal, Extended precision accumulator.
  11. Stribaek,Morten; Paillier,Pascal, Extended-precision accumulation of multiplier output.
  12. Chaudhry,Shailender; Tremblay,Marc, Facilitating value prediction to support speculative program execution.
  13. Kelley, John; Ho, Ying-Wai, Floating-point processor with improved intermediate result handling.
  14. Ho,Ying wai; Jiang,Xing Yu, Floating-point processor with operating mode having improved accuracy and high performance.
  15. Hoffjann, Claus; Schuldzig, Hansgeorg; Westenberger, Andreas, Hybrid drive for an aircraft.
  16. Joel Springer Emer ; Bruce Edwards ; Daniel Lawrence Leibholz ; Edward J. McLellan ; Derrick R. Meyer, Implementation of a conditional move instruction in an out-of-order processor.
  17. Dooley, Miles R.; Indukuru, Venkat R.; Mericas, Alex E.; O'Connell, Francis P., Ineffective prefetch determination and latency optimization.
  18. Ukai, Masaki, Instruction fetch control device and method thereof with dynamic configuration of instruction buffers.
  19. Sonnelitter, III, Robert J.; Alexander, Gregory W.; Prasky, Brian R., Management of cache replacement status in cache memory.
  20. Rozas, Guillermo J.; D'Souza, Godfrey P.; Price, Charles R.; Serris, Paul S., Method and apparatus for enhancing scheduling in an advanced microprocessor.
  21. Rozas, Guillermo J.; D'Souza, Godfrey P.; Price, Charles R.; Serris, Paul S., Method and apparatus for enhancing scheduling in an advanced microprocessor.
  22. Rozas,Guillermo J.; D'Souza,Godfrey P.; Price,Charles R.; Serris,Paul S., Method and apparatus for enhancing scheduling in an advanced microprocessor.
  23. Jiang, XingYu; Ho, Ying-wai; Kelley, John L., Method and apparatus for predicting floating-point exceptions.
  24. Tremblay, Marc; Chaudhry, Shailender; Jacobson, Quinn A., Method and structure for explicit software control using scoreboard status information.
  25. Johnson, Richard; Rozas, Guillermo, Method for increasing the speed of speculative execution.
  26. Johnson, Richard; Rozas, Guillermo, Method for increasing the speed of speculative execution.
  27. van Hook,Timothy; Hsu,Peter; Huffman,William A.; Moreton,Henry P.; Killian,Earl A., Method for providing extended precision in SIMD vector arithmetic operations.
  28. Drabenstott, Thomas L.; Pechanek, Gerald G.; Barry, Edwin F.; Kurak, Jr., Charles W., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
  29. Stribaek, Morten; Kissell, Kevin D.; Paillier, Pascal, Microprocessor instructions for performing polynomial arithmetic operations.
  30. Shimada, Sachiko, Parallel processing apparatus.
  31. Puzak,Thomas R.; Hartstein,Allan M.; Charney,Mark; Prener,Daniel A.; Oden,Peter H., Prefetching using future branch path information derived from branch prediction.
  32. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having a compare extension of an instruction set architecture.
  33. Thekkath,Radhika; Uhler,G. Michael; Ho,Ying wai; Harrell,Chandlee B., Processor having a compare extension of an instruction set architecture.
  34. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having a conditional branch extension of an instruction set architecture.
  35. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having an arithmetic extension of an instruction set architecture.
  36. Ho, Ying-wai; Kelley, John L.; Jiang, XingYu, Processor with improved accuracy for multiply-add operations.
  37. Ho,Ying wai; Kelley,John L.; Jiang,XingYu, Processor with improved accuracy for multiply-add operations.
  38. Van Hook, Timothy J.; Hsu, Peter; Huffman, William A.; Moreton, Henry P.; Killian, Earl A., Providing extended precision in SIMD vector arithmetic operations.
  39. Wang, Hong; Aamodt, Tor M.; Marcuello, Pedro; Stark, IV, Jared W.; Shen, John P.; Gonzalez, Antonio; Hammarlund, Per; Hoflehner, Gerolf F.; Wang, Perry H.; Liao, Steve Shih-wei, Speculative multi-threading for instruction prefetch and/or trace pre-build.
  40. Wang, Hong; Aamodt, Tor M.; Marcuello, Pedro; Stark, IV, Jared W.; Shen, John P.; González, Antonio; Hammarlund, Per; Hoflehner, Gerolf F.; Wang, Perry H.; Liao, Steve Shih-wei, Speculative multi-threading for instruction prefetch and/or trace pre-build.
  41. Kissell, Kevin D., Substituting portion of template instruction parameter with selected virtual instruction parameter.
  42. Kalluri,Seshagiri P.; Trombetta,Ramon C.; Krolnik,Adam C., System and method for cooperative execution of multiple branching instructions in a processor.
  43. Wichman,Shannon A.; Kalluri,Seshagiri Prasad, System and method for executing software program instructions using a condition specified within a conditional execution instruction.
  44. Ho, Ying-wai; Schulte, Michael J.; Kelley, John L., System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit.
  45. Holscher, Brian; Rozas, Guillermo; Van Zoeren, James; Dunn, David, Systems and methods for reordering processor instructions.
  46. Kissell, Kevin D., Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution.
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