초록 ▼

A Single Electron MOS Memory (SEMM), in which one bit of information is represented by storing only one electron, has been demonstrated at room temperature. The SEMM is a floating gate Metal-Oxide-Semiconductor (MOS) transistor in silicon with a channel width (about 10 nanometers) which is smaller t

A Single Electron MOS Memory (SEMM), in which one bit of information is represented by storing only one electron, has been demonstrated at room temperature. The SEMM is a floating gate Metal-Oxide-Semiconductor (MOS) transistor in silicon with a channel width (about 10 nanometers) which is smaller than the Debye screening length of a single electron stored on the floating gate, and a nanoscale polysilicon dot (about 7 nanometers by 7 nanometers by 2 nanometers) as the floating gate which is positioned between the channel and the control gate. An electron stored on the floating gate can screen the entire channel from the potential on the control gate, and lead to: (i) a discrete shift in the threshold voltage; (ii) a staircase relation between the charging voltage and the shift; and (iii) a self-limiting charging process. The structure and fabrication of the SEMM is well adapted to the manufacture of ultra large-scale integrated circuits.

대표청구항 ▼

[ What is claimed is:] [1.] A data storage device, comprising:(a) a source-to-drain path including a channel region between a source and a drain, the channel region being comprised of a semiconductor;(b) a single floating gate for storing at least one charge carrier, the floating gate being disposed

[ What is claimed is:] [1.] A data storage device, comprising:(a) a source-to-drain path including a channel region between a source and a drain, the channel region being comprised of a semiconductor;(b) a single floating gate for storing at least one charge carrier, the floating gate being disposed over the channel region and isolated from the channel region by a first gate dielectric layer having a thickness of about 1 nanometer; and(c) a control gate disposed over the floating gate and isolated from the floating gate by a second gate dielectric layer so that a single charge carrier on the floating gate at room temperature produces a significant shift in threshold voltage of the channel region with respect to the control gate.