초록 ▼

Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, whe

Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.

대표청구항 ▼

[ What is claimed is:] [1.] A method for forming a multi-level interconnect in an integrated circuit comprising a conductor, a cap dielectric layer, and a low-k dielectric layer, said method comprising the steps of:depositing a first hard mask layer over the low-k dielectric layer;depositing a secon

[ What is claimed is:] [1.] A method for forming a multi-level interconnect in an integrated circuit comprising a conductor, a cap dielectric layer, and a low-k dielectric layer, said method comprising the steps of:depositing a first hard mask layer over the low-k dielectric layer;depositing a second hard mask layer over said first hard mask layer, wherein said second hard mask layer exhibits etch-selectivity with respect to the cap dielectric layer and the low-k dielectric layer, and said first hard mask layer is resistant to polishing-induced erosion;polishing said second hard mask layer such that said second hard mask layer is substantially removed, and said first hard mask layer is substantially intact.