초록 ▼

A clock control type information processing apparatus of the invention selects clock frequency according to load state, which reduces electric power consumption without substantially reducing the effective performance of the program. The clock control type information processing apparatus including

A clock control type information processing apparatus of the invention selects clock frequency according to load state, which reduces electric power consumption without substantially reducing the effective performance of the program. The clock control type information processing apparatus including a central processing unit for executing programs and a plurality of peripheral processing units connected to the central processing unit using a bus, includes a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing units, a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing units; and a clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus.

대표청구항 ▼

[ What is claimed is:] [1.] A clock control type information processing apparatus including a central processing unit for executing programs and at least one peripheral processing unit connected to the central processing unit using a bus comprising:a clock generating unit for generating clock signal

[ What is claimed is:] [1.] A clock control type information processing apparatus including a central processing unit for executing programs and at least one peripheral processing unit connected to the central processing unit using a bus comprising:a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing unit;a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing unit; anda clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus such that one of at least a first, second, and third clock frequency is generated according to a corresponding first, second, and third load state of the bus.