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Flip-chip having electrical contact pads on the backside of the chip 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/02
출원번호 US-0227650 (1999-01-08)
발명자 / 주소
  • McMahon John F.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 59  인용 특허 : 7

초록 ▼

An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite the first surface. Circuit elements are formed within the first surface. A plurality of bump contacts are located on the first surface and connected to

대표청구항 ▼

[ What is claimed:] [16.] An apparatus comprising:a semiconductor substrate having a first surface and a second surface opposite said first surface;circuit elements disposed within said first surface;a conductor region located over said first surface having a top-side surface;a first plurality of co

이 특허에 인용된 특허 (7)

  1. Little Michael J. (Woodland Hills CA) Grinberg Jan (Los Angeles CA) Garvin Hugh L. (Malibu CA), 3-D integrated circuit assembly employing discrete chips.
    상세보기
  2. Padmanabhan Gobi R., Array of solder pads on an integrated circuit.
    상세보기
  3. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  4. Rostoker Michael D. (Boulder Creek CA) Kapoor Ashok K. (Palo Alto CA), Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures.
    상세보기
  5. Hause James V. (Phoenix AZ), Method of manufacturing a bonding pad structure.
    상세보기
  6. Santadrea Joseph F. (Los Altos Hills CA) Lee Ji-Min (Palo Alto CA) Lien Chuen-Der (Mountain View CA) Huggins Alan H. (Gilroy CA), Parallel manufacturing of semiconductor devices and the resulting structure.
    상세보기
  7. Imaoka Toshikazu,JPX ; Imai Nobuaki,JPX, Semiconductor device provided with surface grounding conductor for covering surfaces of electrically insulating films.
    상세보기

이 특허를 인용한 특허 (59)

  1. Bobba, Sudhakar; Thorp, Tyler; Trivedi, Pradeep, 180 degree bump placement layout for an integrated circuit power grid.
    상세보기
  2. Lam, Ken M., Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package.
    상세보기
  3. Kramer Alan H. ; Thomas Danielle A., Backside bus vias.
    상세보기
  4. John A. Iacoponi ; John C. Miethke, Backside contact for integrated circuit and method of forming same.
    상세보기
  5. Thomas Danielle A., Backside contact for touchchip.
    상세보기
  6. Thomas,Danielle A., Backside contact for touchchip.
    상세보기
  7. Fan,Chun Ho; McLellan,Neil; Tsang,Kwok Cheung, Ball grid array package and process for manufacturing same.
    상세보기
  8. McLellan, Neil; Sze, Ming Wang; Lam, Wing Keung; Wong, Kin-wai, Ball grid array package with improved thermal characteristics.
    상세보기
  9. McLellan, Neil; Sze, Ming Wang; Tsang, Kwok Cheung; Lam, Wing Keung; Tam, Wai Kit, Ball grid array package with improved thermal characteristics.
    상세보기
  10. Lu, Szu Wei; Lii, Mirng-Ji; Chen, Chen-Shien; Wu, Hua-Shu; Tzou, Jerry, Bonding structures and methods of forming bonding structures.
    상세보기
  11. Chu, Tse-Ming; Ma, Sung-Chuan, Chip package structure with ENIG plating.
    상세보기
  12. Thomas H. DiStefano ; John W. Smith, Chip with internal signal routing in external element.
    상세보기
  13. Yoji Suzuki JP, Compound semiconductor device.
    상세보기
  14. Hedler, Harry; Haimerl, Alfred, Electronic component with flexible bonding pads and method of producing such a component.
    상세보기
  15. Lam, Ken M., Electronics package with an integrated circuit device having post wafer fabrication integrated passive components.
    상세보기
  16. Andry, Paul S.; Cooney, III, Edward C.; Sprogis, Edmund J.; Stamper, Anthony K.; Tsang, Cornelia K., Electrostatic chucking of an insulator handle substrate.
    상세보기
  17. Mak Tak M. ; Winer Paul ; Rao Valluri R. ; Livengood Richard H., Flip-chip having an on-chip decoupling capacitor.
    상세보기
  18. Rogers, Harvey Newell; Kintis, Mark, Inexpensive wafer level MMIC chip packaging.
    상세보기
  19. Meyer-Berg, Georg; Daeche, Frank, Integrated circuit package and a method for manufacturing an integrated circuit package.
    상세보기
  20. Meyer-Berg, Georg; Daeche, Frank, Integrated circuit package and packaging methods.
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  21. Lu,Szu Wei; Tzou,Jerry, Interconnect structure for semiconductor package.
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  22. Akagawa, Masatoshi, Method for manufacturing semiconductor device.
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  23. Chen I-Ming,TWX, Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate.
    상세보기
  24. Chen I-Ming,TWX, Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate.
    상세보기
  25. Iadanza, Joseph A., Method of connecting core I/O pins to backside chip I/O pads.
    상세보기
  26. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.
    상세보기
  27. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.
    상세보기
  28. Kramer, Alan H.; Thomas, Danielle A., Method of forming backside bus vias.
    상세보기
  29. Duesman, Kevin G.; Farnworth, Warren M., Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections.
    상세보기
  30. Sheats, James, Method of packaging and interconnection of integrated circuits.
    상세보기
  31. Hedler, Harry; Haimerl, Alfred, Method of producing an electronic component with flexible bonding.
    상세보기
  32. Thomas P. Glenn ; Steven M. Anderson, Module of stacked integrated circuit packages including an interposer.
    상세보기
  33. DiStefano, Thomas H.; Smith, John W., Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element.
    상세보기
  34. Rissing, Lutz; Siglbauer, Dietmar, Optoelectronic system and method for its manufacture.
    상세보기
  35. Chun Chan ; Bo Shen, Power mesh bridge.
    상세보기
  36. Fukada,Masakazu; Nakajima,Dai; Takanashi,Ken, Power module.
    상세보기
  37. Masakazu Fukada JP; Dai Nakajima JP; Ken Takanashi JP, Power module.
    상세보기
  38. Daido, Yukiko, Printed wiring board for attachment to a socket connector, having recesses and conductive tabs.
    상세보기
  39. Leib, Juergen, Process for packaging components, and packaged components.
    상세보기
  40. Leib, Juergen, Process for packaging components, and packaged components.
    상세보기
  41. Cook Duane ; Murali Venkatesan ; Ramalingam Suresh ; Vodrahalli Nagesh, Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state.
    상세보기
  42. Brooks, Jerry M., Semiconductor assembly without adhesive fillets.
    상세보기
  43. Azuma, Kosuke, Semiconductor chip mounting structure with movable connection electrodes.
    상세보기
  44. Akagawa, Masatoshi, Semiconductor device and manufacturing method therefor.
    상세보기
  45. Kamikuri, Koichi; Shibue, Hitoshi, Semiconductor device and semiconductor device structure.
    상세보기
  46. Kurita, Yoichiro, Semiconductor device with a dummy electrode.
    상세보기
  47. Searls, Damion T.; Dujari, Prateek J.; Lian, Bin, Semiconductor device with components embedded in backside diamond layer.
    상세보기
  48. Richter, Daniel; Kuechenmeister, Frank, Semiconductor dies with reduced area consumption.
    상세보기
  49. Tsai,Chen Jung; Lee,Jui Chung; Lin,Chih Wen, Semiconductor packaging device and manufacture thereof.
    상세보기
  50. Ozguz, Volkan; Pepe, Angel; Yamaguchi, James; Boyd, W. Eric; Albert, Douglas; Camien, Andrew, Stackable semiconductor chip layer comprising prefabricated trench interconnect vias.
    상세보기
  51. Lam, Ken, Stacked-die electronics package with planar and three-dimensional inductor elements.
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  52. Lee,Hsin Hui, Structures and methods for heat dissipation of semiconductor integrated circuits.
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  53. Bailey, Mark J.; Shea, Michael John; Swift, Gerald Wayne, Surface laminar circuit board having pad disposed within a through hole.
    상세보기
  54. Culler, Jason Harold; Shepston, Shad R., System and method for providing compliant mapping between chip bond locations and package bond locations for an integrated circuit.
    상세보기
  55. Chen, Hsien-Wei, System in package (SIP) structure.
    상세보기
  56. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
    상세보기
  57. Heenan, Bryan Timothy, Vertical cache configuration.
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  58. Honer, Kenneth Allen; Humpston, Giles; Tuckerman, David B.; Nystrom, Michael J., Wire bonded wafer level cavity package.
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  59. Honer,Kenneth Allen; Humpston,Giles; Tuckerman,David B.; Nystrom,Michael J., Wire bonded wafer level cavity package.
    상세보기

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