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[미국특허] Semiconductor die package for mounting in horizontal and upright configurations 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/04
출원번호 US-0033480 (1998-03-03)
발명자 / 주소
  • Crane
  • Jr. Stanford W.
  • Krishnapura Lakshminarasimha
출원인 / 주소
  • Silicon Bandwidth, Inc.
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 15  인용 특허 : 30

초록

A semiconductor die package includes a housing and a plurality of leads extending through openings in the housing. The package is designed to be mounted to a printed circuit board in both a horizontal configuration and in an upright configuration. In the horizontal configuration, the face of the die

대표청구항

[ What is claimed is:] [1.] A semiconductor die package comprising:a housing for holding at least one semiconductor die; anda plurality of L-shaped, electrically-conductive leads extending from the housing, each of said leads having a side surface for surface mounting to a printed circuit board when

이 특허에 인용된 특허 (30) 인용/피인용 타임라인 분석

  1. Frei John K. (Mesa AZ) Brice-Heames Kenneth (Mesa AZ), Apparatus for adapting semiconductor die pads and method therefor.
  2. Sucheski Matthew M. (Harrisburg PA) Barkus Lee A. (Millersburg PA), Coaxial contact element.
  3. Kondo Mitsuhiro (Oogaki JPX) Watanabe Osamu (Oogaki JPX), Encapsulated semiconductor device with bridge sealed lead frame.
  4. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  5. Shaheen Joseph M. (La Habra CA) Yamaguchi James S. (Lake Forest CA), Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture.
  6. Frankeny, Jerome A.; Frankeny, Richard F.; Haj-Ali-Ahmadi, Javad; Hermann, Karl; Imken, Ronald L., High density interconnect strip.
  7. Lee Joon K. (Seoul KRX) Jeong Hyeon J. (Inchon KRX) Kim Kyung S. (Seoul KRX) Kwon Oh-Sik (Seoul KRX), High density vertically mounted semiconductor package.
  8. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  9. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  10. Nelson Gregory H. (Gilbert AZ) Lebow Sanford (Westlake CA) Nogavich Eugene (Gilbert AZ), Interconnect device and method of manufacture thereof.
  11. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  12. Shaffer Howard R. (Millersburg PA), Limited insertion force contact terminals and connectors.
  13. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method and apparatus for making printed circuit boards.
  14. Simard Patrice Y. (Eatontown NJ), Method for pattern recognition using prototype transformations and hierarchical filtering.
  15. Gregoire George D. (San Diego CA), Method of mounting a surface-mountable IC to a converter board.
  16. Reylek Robert S. (St. Paul MN) Thompson Kenneth C. (St. Paul MN), Miniature multiple conductor electrical connector.
  17. Taniuchi Kenjiro (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX) Ishikawa Kouji (Kawasaki JPX) Watanabe Kouji (Kawasaki JPX), Mounting device for mounting an electronic device on a substrate by the surface mounting technology.
  18. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
  19. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  20. Hirano Naohiko (Yokohama JPX), Multilayer package.
  21. Tillotson John (Southfield MI), Multiple contact header assembly.
  22. Buck Jonathan E. (Harrisburg PA) Rose William H. (Harrisburg PA), Paired contact electrical connector system.
  23. Shirling David J. (Waterbury CT), Pin grid array having seperate posts and socket contacts.
  24. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
  25. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  26. Kohara Masanobu (Itami JPX) Kondo Takashi (Itami JPX) Yama Yomiyuki (Itami JPX), Semiconductor device and package.
  27. Jurista Thomas M. (Vestal NY) Mantilla Osvaldo A. (Endicott NY), Sequential Connecting device.
  28. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  29. Ishikawa Toru (Tokyo JPX), Surface mount semiconductor device.
  30. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.

이 특허를 인용한 특허 (15) 인용/피인용 타임라인 분석

  1. Xue, Xiaojie; Raleigh, Carl, Apparatus and method for microelectromechanical systems device packaging.
  2. Otremba, Ralf, Device including two mounting surfaces.
  3. Otremba, Ralf, Device including two mounting surfaces.
  4. Do Bento Vieira, Antonio, Method for packaging a semiconductor chip containing sensors and resulting package.
  5. Lee, Tzung-Han; Lin, Kun-Chi, Multi-die package.
  6. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  7. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  8. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  9. Egitto,Frank D.; Farquhar,Donald S.; Markovich,Voya R.; Poliks,Mark D.; Powell,Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  10. Hashiba, Hitoshi, Multichip sensor.
  11. Crane, Jr., Sanford W.; Krishnapura, Lakshminarasimha; Li, Yun, Open-cavity semiconductor die package.
  12. Stanford W. Crane, Jr. ; Lakshminarasimha Krishnapura ; Yun Li, Open-cavity semiconductor die package.
  13. Imoto, Yuji; Yoshimatsu, Naoki; Fujino, Junji, Semiconductor device and method for manufacturing the same.
  14. Caesar, Thomas; Tapper, Renate; Heinz, Steffen; Neubert, Marco, Sensor.
  15. Martizon, Jr., Arturo; Goida, Thomas M., Two-axis vertical mount package assembly.

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