초록 ▼

A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that compri

A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

대표청구항 ▼

[ What is claimed is:] [4.] A multi-port buffer providing multi-level caching, comprising:a Firewire to VME/VXI interface;a Firewire link layer controller;a VME/VXI interface;buffer management logic, comprised of:a plurality of data ports;a plurality of FIFO buffers, wherein there is at least one FI

[ What is claimed is:] [4.] A multi-port buffer providing multi-level caching, comprising:a Firewire to VME/VXI interface;a Firewire link layer controller;a VME/VXI interface;buffer management logic, comprised of:a plurality of data ports;a plurality of FIFO buffers, wherein there is at least one FIFO buffer each for each said data port of said multi-port buffer, and wherein said FIFO buffers may comprise any of input and output buffers; andsequencing logic therefor; anda random access memory (RAM) for caching data routed to and from said FIFO buffers via said ports; anda microprocessor for moving data into and out of said RAM from one of said ports;wherein said microprocessor writes Firewire header information to said link layer controller when sending a data packet,wherein said microprocessor writes data to said RAM and/or instructs said interface and said buffer management logic to read data from a VXI device into said RAM, andwherein said microprocessor then instructs said link layer controller to send said Firewire packet.