초록 ▼

A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DR

A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.

대표청구항 ▼

[ What is claimed is:] [1.] A memory device comprising on a single chip:multiple data ports for providing data input and output,a main memory for storing data,a cache memory coupled between said multiple data ports and said main memory and having a smaller storage capacity than said main memory,addr

[ What is claimed is:] [1.] A memory device comprising on a single chip:multiple data ports for providing data input and output,a main memory for storing data,a cache memory coupled between said multiple data ports and said main memory and having a smaller storage capacity than said main memory,address pins arranged on said chip to provide address information for performing data transfer between said main memory and said cache memory independently of data transfer between said data port and said cache memory, said address pins including separate cache memory address pins arranged for each port of said multiple data ports for addressing the cache memory so as to support independent data transfer between said each port and said cache memory,said address pins being supplied with control values for providing commands to execute various operations, andmain memory address pins for addressing the data transfer between said cache memory and said main memory.