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Integrated circuit with field programmable and application specific logic areas 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H03K-019/177
출원번호 US-0176017 (1998-10-20)
발명자 / 주소
  • Tavana Danesh
  • Yee Wilson K.
  • Trimberger Stephen M.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Young
인용정보 피인용 횟수 : 119  인용 특허 : 6

초록

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int

대표청구항

[ What is claimed is:] [1.] A monolithic integrated circuit comprising:an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and c

이 특허에 인용된 특허 (6)

  1. Chang Web (39939 Stevenson Common ; V-2133 Fremont CA 94538), Application specific field programmable gate array.
  2. Carter William S. (Santa Clara CA), Configurable logic element.
  3. Cox William D. (San Jose CA) Blair Benjamin W. (San Jose CA) Kolze Paige A. (San Jose CA) Chua Hua-Thye (Los Altos CA), Logic module for field programmable gate array.
  4. Buch Kiran B. (Fremont CA) Law Edwin S. (Saratoga CA) Chu Jakong J. (Santa Clara CA), Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays.
  5. Fisher Barbara J. (Palm Bay FL), Programmable array logic with shared product terms and J-K registered outputs.
  6. Mahoney John E. (San Jose CA), Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-c.

이 특허를 인용한 특허 (119)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  11. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  12. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  13. Heidari-Bateni, Ghobad; Plunkett, Robert Thomas, Adaptive, multimode rake receiver for dynamic search and multipath reception.
  14. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  21. Chua, Kar Keng; Cheung, Sammy; Phoon, Hee Kong; Tan, Kim Pin; Goay, Wei Lian, Application-specific integrated circuit equivalents of programmable logic and associated methods.
  22. Chua, Kar Keng; Cheung, Sammy; Phoon, Hee Kong; Tan, Kim Pin; Goay, Wei Lian, Application-specific integrated circuit equivalents of programmable logic and associated methods.
  23. Chua, Kar Keng; Cheung, Sammy; Phoon, Hee Kong; Tan, Kim Pin; Goay, Wei Lian, Application-specific integrated circuit equivalents of programmable logic and associated methods.
  24. Chua,Kar Keng; Cheung,Sammy, Application-specific integrated circuit equivalents of programmable logic and associated methods.
  25. Moore,Michael T.; Lie,James, Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD).
  26. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.
  27. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  28. de Waal, Abraham B.; Diard, Franck R., Automatic quality testing of multimedia rendering by software drivers.
  29. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  30. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  31. Crabill, Eric J., Configurable processor system.
  32. Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
  33. Manohararajah, Valavan; Lewis, David, Configuring programmable integrated circuit device resources as processing elements.
  34. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba, Consumer product distribution in the embedded system market.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  36. Kim,Sang Soo; Oh,Choong Seob; Park,Jin Hyeok; Park,Jin Ho; Kim,Dong Gyu; Park,Yong Eun; Kang,Nam Soo; Lee,Gyu Su, Display panel with signal transmission patterns.
  37. Stoica,Adrian; Salazar Lazaro,Carlos Harold, Evolutionary technique for automated synthesis of electronic circuits.
  38. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  39. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  40. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  41. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  42. Sun, Albert; Sheu, Eric; Lo, Ying-Che, Four state programmable interconnect device for bus line and I/O pad.
  43. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  44. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  45. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  46. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  47. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  48. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James, Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.
  49. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  50. Bemanian, Majid; Scharf, William D.; Entin, Bruce L., Integrated circuit having integrated programmable gate array and field programmable gate array, and method of operating the same.
  51. Bemanian, Majid; Scharf, William D., Integrated circuit having integrated programmable gate array and method of operating the same.
  52. Chan, Jiunn Wen; Schleicher, II, James G.; Patel, Kamal, Interactive tool for contemporaneous design of integrated circuits having different device packages.
  53. Coppola, Alan J.; Stanley, Joel; Wilton, Steven J. E., Interface scheme for connecting a fixed circuitry block to a programmable logic core.
  54. Coppola, Alan J.; Stanley, Joel; Wilton, Steven J. E., Interface scheme for connecting a fixed circuitry block to a programmable logic core.
  55. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.
  56. Kim, Sang-Soo; Oh, Choong-Seob; Park, Jin-Hyeok; Park, Jin-Ho; Kim, Dong-Gyu; Park, Yong-Eun; Kang, Nam-Soo; Lee, Gyu-Su, Liquid crystal display panel with signal transmission patterns.
  57. Kim,Sang Soo; Oh,Choong Seob; Park,Jin Hyeok; Park,Jin Ho; Kim,Dong Gyu; Park,Yong Eun; Kang,Nam Soo; Lee,Gyu Su, Liquid crystal display panel with signal transmission patterns.
  58. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  59. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  60. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  61. Tan,Kim Pin; Ang,Boon Jin; Ng,Bee Yee, Mask-programmable logic device with building block architecture.
  62. Lawson,Jimmy; Karchmer,David; Khalaf,Marwan A, Mask-programmable logic device with programmable portions.
  63. Lawson,Jimmy; Karchmer,David; Khalaf,Marwan A., Mask-programmable logic device with programmable portions.
  64. Park, Jonathan, Mask-programmable logic devices with programmable gate array sites.
  65. Fogal,Rich; Reynolds,Tracy; Cowles,Timothy, Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device.
  66. Park, Jonathan, Method and apparatus for providing clock/buffer network in mask-programmable logic device.
  67. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  68. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  69. Allegrucci, Jean-Didier, Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory.
  70. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  71. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  72. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  73. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  74. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  75. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  76. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  77. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  78. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.
  79. Wilton,Steven J E; Bozman,Kimberly; Kafafi,Noha; Wu,James, Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith.
  80. Wilton,Steven J. E.; Bozman,Kimberly; Kafafi,Noha; Wu,James, Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith.
  81. Perry, Steven; Nixon, Gregor; Kong, Larry; Scott, Alasdair; Hall, Andrew; Wang, Lingli; Dettmar, Chris; Park, Jonathan; Price, Richard, Method for programming a mask-programmable logic device and device so programmed.
  82. Perry,Steven; Nixon,Gregor; Kong,Larry; Scott,Alasdair; Hall,Andrew; Wang,Lingli; Dettmar,Chris; Park,Jonathan; Price,Richard, Method for programming a mask-programmable logic device and device so programmed.
  83. Tharmalingam,Kumara, Method for programming programmable logic device having specialized functional blocks.
  84. Parry, Stuart; Stansfield, Anthony, Method of configuring embedded application-specific functional blocks.
  85. Park, Jonathan; Chen, Eugen; Saito, Richard; Wright, Adam; Ratchev, Evgueni, Method of creating a mask-programmed logic device from a pre-existing circuit design.
  86. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  87. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  88. Yuan,Jinyong; Chua,Kar Keng; Park,Ji, Methods for creating and expanding libraries of structured ASIC logic and other functions.
  89. Yuan,Jinyong, Methods for improved structured ASIC design.
  90. Schleicher, II,James G.; Karchmer,David, Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits.
  91. Schleicher, II, James G.; Karchmer, David, Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits.
  92. Schleicher, II,James G; Yuan,Jinyong, Methods for producing equivalent logic designs for FPGAs and structured ASIC devices.
  93. Pedersen,Bruce; Yuan,Jinyong, Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations.
  94. Tan,Kim Pin; Chua,Kar Keng, Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays.
  95. Park,Ji; Yuan,Jinyong; Chua,Kar Keng; Puchkaryov,Evgenii, Methods for storing and naming static library cells for lookup by logic synthesis and the like.
  96. Yuan, Jinyong; Park, Ji, Methods of verifying functional equivalence between FPGA and structured ASIC logic cells.
  97. Yuan,Jinyong; Park,Ji, Methods of verifying functional equivalence between FPGA and structured ASIC logic cells.
  98. Barry K. Britton ; Ravikumar Charath ; Zheng Chen ; James F. Hoff ; Cort D. Lansenderfer ; Don McCarley ; Richard G. Stuby, Jr. ; Ju-Yuan D. Yang, Multi-master multi-slave system bus in a field programmable gate array (FPGA).
  99. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell.
  100. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell.
  101. Sun, Albert; Sheu, Eric; Lo, Ying-Che, One cell programmable switch using non-volatile cell with unidirectional and bidirectional states.
  102. Foo,Loke Yip, Optimizing logic in non-reprogrammable logic devices.
  103. van Wageningen,Darren; Wortman,Curt, Output reporting techniques for hard intellectual property blocks.
  104. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  105. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  106. Lewis,David; Cashman,David, Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks.
  107. Lewis,David; Cashman,David, Programmable logic device having redundancy with logic element granularity.
  108. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  109. Kim,Sang Soo; Oh,Choong Seob; Park,Jin Hyeok; Park,Jin Ho; Kim,Dong Gyu; Park,Yong Eun; Kang,Nam Soo; Lee,Gyu Su; Kang,Sin Gu, Signal transmission film and a liquid crystal display panel having the same.
  110. Master,Paul L.; Watson,John, Storage and delivery of device features.
  111. Park,Jonathan, Switch methodology for mask-programmable logic devices.
  112. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  113. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  114. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  115. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  116. Camarota,Rafael; Rahim,Irfan; Ang,Boon Jin; Chong,Thow Pang, Techniques for combining volatile and non-volatile programmable logic on an integrated circuit.
  117. van Wageningen,Darren; Wortman,Curt; Ang,Boon Jin; Chong,Thow Pang; Mansur,Dan; Burney,Ali, Techniques for optimizing design of a hard intellectual property block for data transmission.
  118. van Wageningen,Darren, Techniques for transmitting and receiving SPI4.2 status signals using a hard intellectual property block.
  119. Scott,Alasdair; Nixon,Gregor, Timing analysis for programmable logic.
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