초록 ▼

A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor

A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor using pre-traceback shift registers and traceback memory. The decoder performs n-state Trellis decoding in real time while simultaneously de-interleaving a multiplexed data stream. The architecture can be expanded to provide programmable length traceback in a fixed number of clock cycles. The invention performs de-interleaving in parallel with the Trellis decoding, and symbols coming out of the decoder need no further processing for de-interleaving. Moreover, the invention allows complete traceback in one symbol period at video rates without the need for very high speed clocks or multi-read port memories. Programmability allows for flexible tradeoff of output error rate and traceback memory space.

대표청구항 ▼

[ What is claimed is:] [1.] A trellis decoder for decoding symbol data from a trellis-encoded input data stream, the data stream comprising a stream of symbols being passed once per symbol period, the decoder comprising:a) branch metric generator means for generating branch metric values from the tr

[ What is claimed is:] [1.] A trellis decoder for decoding symbol data from a trellis-encoded input data stream, the data stream comprising a stream of symbols being passed once per symbol period, the decoder comprising:a) branch metric generator means for generating branch metric values from the trellis-encoded input data stream, having an input for accepting the trellis-encoded input data stream, and a data output comprising branch metric values generated from the data on the input data stream;b) a plurality of add/compare/select modules for computing path metric values from branch metric data, each having an input coupled to the data output of the branch metric generator, a memory connection for retrieving stored path metrics from a path metric memory and a selection output;c) one path metric memory for each add/compare/select module, each path metric memory having a data input and an address input, and an output coupled to the memory connection of one add/compare/select module, each path metric memory comprising a plurality of storage locations addressed by the address input;d) a shuffler having a plurality of inputs coupled to the selection outputs of the add/compare/select module and a plurality of outputs each coupled to the data input of a path metric memory, such that the selection output from the add/compare/select modules is sorted and provided to the path metric memories, and written to the storage location in the path metric memory addressed by the address input of the path metric memory; ande) a traceback processor.