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Methods and structures for gold interconnections in integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/764
출원번호 US-0188970 (1998-11-10)
발명자 / 주소
  • Forbes Leonard
  • Farrar Paul A.
  • Ahn Kie Y.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 17  인용 특허 : 34

초록

A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum t

대표청구항

[ What is claimed is:] [1.] A self-planarizing method of making a gold structure, the method comprising:forming a first layer including silicon and germanium;oxidizing a region of the first layer to define an oxidized region and a non-oxidized region; andsubstituting gold for at least a portion of t

이 특허에 인용된 특허 (34)

  1. Lee Kyu-Woong (Arlington MA) Durschlag Mark S. (Natick MA) Day John (Lexington MA), Evaporated thick metal and airbridge interconnects and method of manufacture.
  2. Kermani Ahmad (Fremont CA) Johnsgard Kristian E. (San Jose CA) Galewski Carl (Berkeley CA), Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure.
  3. Wu Zhiqiang ; Pan Pai-Hung, Gate stack with improved sidewall integrity.
  4. Mitchell Curtis W. (Scottsdale AZ) Johnson Barry C. (Tempe AZ), Gold metallization process.
  5. Prasad Jayasimha S. (Tigard OR) Park Song W. (Aloha OR) Vetanen William A. (Sherwood OR) Beers Irene G. (Sherwood OR) Haynes Curtis M. (Portland OR), Implant-free heterojunction bioplar transistor integrated circuit process.
  6. Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  7. Prall Kirk D. (Boise ID) Sandhu Gurtej S. (Boise ID) Meikle Scott G. (Boise ID), Low resistance device element and interconnection structure.
  8. Pfiester James R. (Austin TX) Tobin Philip J. (Austin TX), Method for forming electrical isolation in an integrated circuit device.
  9. Farrar Paul A. ; Forbes Leonard, Method for making high-Q inductive elements.
  10. Klatskin Jerome Barnard (Princeton Junction NJ) Rosen Arye (Cherry Hill NJ), Method of electrically interconnecting semiconductor elements.
  11. Tam Gordon (Chandler AZ) Granick Lisa R. (Philadelphia PA), Method of fabricating airbridge metal interconnects.
  12. Farrar Paul A., Method of forming a support structure for air bridge wiring of an integrated circuit.
  13. Chen Fusen E. (Dallas TX) Liou Fu-Tai (Carrollton TX) Dixit Girish A. (Dallas TX), Method of forming vias.
  14. Chino Toyoji (Osaka JPX) Matsuda Kenichi (Osaka JPX) Shibata Jun (Osaka JPX), Method of making semiconductor device with air-bridge interconnection.
  15. Forbes Leonard ; Farrar Paul A. ; Ahn Kie Y., Methods and structures for gold interconnections in integrated circuits.
  16. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  17. Nakano Hirofumi (Itami JPX), Multi-layer wiring.
  18. Danek Michal ; Levy Karl B., Multilayer diffusion barriers.
  19. Aboelfotoh Mohamed Osama ; Krusin-Elbaum Lia ; Sun Yuan-Chen, Multilevel electronic structures containing copper layer and copper-semiconductor layers.
  20. Lee Sangin (Suwon KRX) Park Soonoh (Seoul KRX), Ohmic contact structure of a highly integrated semiconductor device having two resistance control layers formed between.
  21. Yoshida Katsuhito (Hyogo JPX) Tsuji Kazuwo (Hyogo JPX), Ohmic electrode for n-type cubic boron nitride and the process for manufacturing the same.
  22. Rogers Michael R. (Santa Clara County CA) Washburn Theodore E. (South Barrington IL) Novice Michael A. (Santa Clara County CA) Besser Ronald S. (San Mateo County CA) White Brian S. (Alameda County CA, Process for forming solid conductive vias in substrates.
  23. Miura Takao,JPX ; Yamauchi Tunenori,JPX ; Monma Yoshinobu,JPX ; Goto Hiroshi,JPX, Process for manufacturing semiconductor devices separated by an air-bridge.
  24. Gardner Donald S., Process of fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circu.
  25. Klose Helmut,DEX ; Weber Werner,DEX ; Bertagnolli Emmerich,DEX ; Koppe Siegmar,DEX ; Hubner Holger,DEX, Semiconductor component for vertical integration and manufacturing method.
  26. Inoue Tomotoshi (Kanagawa JPX) Terada Toshiyuki (Tokyo JPX) Tomita Kenichi (Kanagawa JPX), Semiconductor device having an improved air-bridge lead structure.
  27. Ohya Shuichi,JPX ; Sakao Masato,JPX ; Takaishi Yoshihiro,JPX ; Kajiyana Kiyonori,JPX ; Akimoto Takeshi,JPX ; Oguro Shizuo,JPX ; Shishiguchi Seiichi,JPX, Semiconductor memory device having trench isolation regions and bit lines formed thereover.
  28. Hsu Wei-Yung ; Anderson Dirk N. ; Kraft Robert, Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silico.
  29. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Semiconductor structure having an air region and method of forming the semiconductor structure.
  30. Gorowitz Bernard ; Becker Charles Adrian ; Guida Renato ; Gorczyca Thomas Bert ; Rose James Wilson, Structure for protecting air bridges on semiconductor chips from damage.
  31. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  32. Agnello Paul David ; Cabral ; Jr. Cyril ; Grill Alfred ; Jahnes Christopher Vincent ; Licata Thomas John ; Roy Ronnen Andrew, Tasin oxygen diffusion barrier in multilayer structures.
  33. Lemnios Zachary J. (Colorado Springs CO) McIntyre David G. (Colorado Springs CO) Lau Chung-Lim (Colorado Springs CO) Williams Dennis A. (Colorado Springs CO), Three metal personalization of application specific monolithic microwave integrated circuit.
  34. Wu Shye Lin,TWX, Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure..

이 특허를 인용한 특허 (17)

  1. Farrar, Paul A.; Geusic, Joseph E., Aligned buried structures formed by surface transformation of empty spaces in solid state materials.
  2. Farrar, Paul A.; Geusic, Joseph E., Alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
  3. Farrar,Paul A.; Geusic,Joseph, Buried conductor patterns formed by surface transformation of empty spaces in solid state materials.
  4. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride.
  5. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
  6. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
  7. Farrar,Paul A., Interconnect alloys and methods and apparatus using same.
  8. Farrar, Paul A.; Geusic, Joseph E., Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
  9. Farrar, Paul A.; Geusic, Joseph E., Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials.
  10. Paul A. Farrar ; Joseph Geusic, Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials.
  11. Ahn,Kie Y.; Forbes,Leonard; Farrar,Paul A., Methods and structures for metal interconnections in integrated circuits.
  12. Forbes,Leonard; Ahn,Kie Y., Self aligned metal gates on high-k dielectrics.
  13. Forbes,Leonard; Ahn,Kie Y., Self aligned metal gates on high-k dielectrics.
  14. Bhattacharyya, Arup; Farrar, Paul A., Techniques to create low K ILD for BEOL.
  15. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD for BEOL.
  16. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD for beol.
  17. Bhattacharyya,Arup; Farrar,Paul A., Techniques to create low K ILD forming voids between metal lines.
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