초록 ▼

A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one em

A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one embodiment, at least one memory slice configures the PLD into a logic analysis context for providing on-chip testing. In one embodiment, the plurality of logic resources include a plurality of storage elements. State data generated by a user-defined context is stored in the plurality of storage elements. When the trigger logic structure provides a trigger signal, the PLD is reconfigured into the logic analysis context. The logic analysis context reads and processes the state data stored in the plurality of storage elements to test the performance of the user-defined context. In one embodiment, the storage elements are multi-bit micro-registers that store state data generated by a plurality of contexts implemented in the multiple-context PLD.

대표청구항 ▼

[ What is claimed is:] [1.] A programmable logic device (PLD), comprising:a user-configurable logic structure having a plurality of configurable logic resources interconnected by a configurable interconnect structure;a plurality of multi-bit configuration memories coupled to said user-configurable l

[ What is claimed is:] [1.] A programmable logic device (PLD), comprising:a user-configurable logic structure having a plurality of configurable logic resources interconnected by a configurable interconnect structure;a plurality of multi-bit configuration memories coupled to said user-configurable logic structure, wherein each of said multi-bit configuration memories comprises a plurality of configuration memory cells;a configuration control circuit coupled to said plurality of multi-bit configuration memories and configured to select a first set of configuration memory cells to apply to the user-configurable logic structure; anda trigger logic structure coupled to said configuration control circuit and configured to cause the configuration control circuit to select a second set of configuration memory cells to apply to the user-configurable logic structure.