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[미국특허] Method for forming an ohmic electrode 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3205
출원번호 US-0054498 (1998-04-03)
우선권정보 JP-0093674 (1997-04-11)
발명자 / 주소
  • Ota Yorito,JPX
  • Masato Hiroyuki,JPX
  • Kumabuchi Yasuhito,JPX
  • Kitabatake Makoto,JPX
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd., JPX
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 112  인용 특허 : 4

초록

A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first metal film and the substrate and the interface between the second metal film and the substrate both fo

대표청구항

[ What is claimed is:] [1.] A method for forming an ohmic electrode, comprising the steps of:forming an insulator film on a surface of a substrate made of silicon carbide, the insulator film having an opening through which the surface of the substrate is exposed;depositing a metal film in the openin

이 특허에 인용된 특허 (4) 인용/피인용 타임라인 분석

  1. Onishi Takashi,JPX ; Yoshikawa Kazuo,JPX ; Nishi Seiji,JPX ; Yamamoto Seigou,JPX, A1 alloy films and melting A1 alloy sputtering targets for depositing A1 alloy films.
  2. Agarwal Anant K. (Monroeville PA) Messham Rowan L. (Murrysville PA) Driver Michael C. (McKeesport PA), Aluminum gallium nitride based heterojunction bipolar transistor.
  3. Furukawa Katsuki (Sakai JPX) Suzuki Akira (Nara JPX) Shigeta Mitsuhiro (Nara JPX) Uemoto Atsuko (Nara JPX), Electrode structure for silicon carbide semiconductors.
  4. Furukawa Katsuki (Sakai JPX) Suzuki Akira (Nara JPX) Fujii Yoshihisa (Nara JPX), Silicon carbide semiconductor device with ohmic electrode consisting of alloy.

이 특허를 인용한 특허 (112) 인용/피인용 타임라인 분석

  1. Tomoda,Katsuhiro; Ohata,Toyoharu, Alloy method using laser irradiation.
  2. Tomoda, Katsuhiro; Ohata, Toyoharu, Alloying method for a image display device using laser irradiation.
  3. Tomoda,Katsuhiro; Ohata,Toyoharu, Alloying method using laser irradiation for a light emitting device.
  4. Tomoda,Katsuhiro; Ohata,Toyoharu, Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method.
  5. Bai, Jie; Lochtefeld, Anthony J.; Park, Ji-Soo, Defect reduction using aspect ratio trapping.
  6. Bai, Jie; Lochtefeld, Anthony J.; Park, Ji-Soo, Defect reduction using aspect ratio trapping.
  7. Bai, Jie; Park, Ji-Soo; Lochtefeld, Anthony J., Defect reduction using aspect ratio trapping.
  8. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  9. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  10. Lochtefeld, Anthony J., Devices formed from a non-polar plane of a crystalline material and method of making the same.
  11. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  12. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  13. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  14. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  15. Lochtefeld, Anthony J., Diode-based devices and methods for making the same.
  16. Ryu, Sei-Hyung; Agarwal, Anant K.; Ward, Allan, Edge termination structures for silicon carbide devices.
  17. Passlack, Matthias; Hartin, Olin L.; Ray, Marcus; Medendorp, Nicholas, Enhancement mode metal-oxide-semiconductor field effect transistor.
  18. Singh, Ranbir, Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same.
  19. Park, Ji-Soo, Epitaxial growth of crystalline material.
  20. Park, Ji-Soo, Epitaxial growth of crystalline material.
  21. Park, Ji-Soo; Fiorenza, James G., Fabrication and structures of crystalline material.
  22. Vieira,Amarildo J. C.; Barenburg,Barbara F.; Brophy,Timothy J., Fabrication of a wavelength locker within a semiconductor structure.
  23. Liang, Yong; Droopad, Ravindranath; Li, Hao; Yu, Zhiyi, Ferromagnetic semiconductor structure and method for forming the same.
  24. Cheng, Zhiyuan; Fiorenza, James; Hydrick, Jennifer M.; Lochtefeld, Anthony J.; Park, Ji-Soo; Bai, Jie; Li, Jizhong, Formation of devices by epitaxial layer overgrowth.
  25. Hydrick, Jennifer M.; Li, Jizhong; Cheng, Zhinyuan; Fiorenza, James; Bai, Jie; Park, Ji-Soo; Lochtefeld, Anthony J., Formation of devices by epitaxial layer overgrowth.
  26. Cole, Melanie W.; Joshi, Pooran C., Formulation and fabrication of an improved Ni based composite Ohmic contact to n-SiC for high temperature and high power device applications.
  27. Yokogawa, Ken'etsu; Miyake, Masatoshi, Heat treatment apparatus that performs defect repair annealing.
  28. El Zein,Nada; Ramdani,Jamal; Eisenbeiser,Kurt; Droopad,Ravindranath, Heterojunction tunneling diodes and process for fabricating same.
  29. Ye, Peide; Cheng, Zhiyuan; Xuan, Yi; Wu, Yanqing; Adekore, Bunmi; Fiorenza, James, InP-based transistor fabrication.
  30. Ye, Peide; Cheng, Zhiyuan; Xuan, Yi; Wu, Yanqing; Adekore, Bunmi; Fiorenza, James, InP-based transistor fabrication.
  31. Mai, Zhihong; Toh, Suey Li; Tan, Pik Kee; Lam, Jeffrey C.; Hsia, Liang-Choo, Integrated circuit system employing backside energy source for electrical contact formation.
  32. Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures and related methods for device fabrication.
  33. Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures and related methods for device fabrication.
  34. Li, Jizhong; Lochtefeld, Anthony J., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  35. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  36. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  37. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  38. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  39. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  40. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  41. Lochtefeld, Anthony J.; Currie, Matthew T.; Cheng, Zhiyuan; Fiorenza, James; Braithwaite, Glyn; Langdo, Thomas A., Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication.
  42. Li, Jizhong; Lochtefeld, Anthony J., Light-emitter-based devices with lattice-mismatched semiconductor structures.
  43. Slater, Jr., David B.; Edmond, John; Donofrio, Matthew, Localized annealing of metal-silicon carbide ohmic contacts and devices so formed.
  44. Ooms,William J.; Hallmark,Jerald A., Method and apparatus utilizing monocrystalline insulator.
  45. Bruel, Michel, Method and device for heating a layer of a plate by priming and light flow.
  46. Tomoda,Katsuhiro; Ohata,Toyoharu, Method for alloying a wiring portion for a image display device.
  47. Ramdani, Jamal; Droopad, Ravindranath; Yu, Zhiyi, Method for fabricating a semiconductor structure including a metal oxide interface with silicon.
  48. Liang,Yong; Droopad,Ravindranath; Hu,Xiaoming; Wang,Jun; Wei,Yi; Yu,Zhiyi, Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process.
  49. Li, Hao; Droopad, Ravindranath; Marshall, Daniel S.; Wei, Yi; Hu, Xiao M.; Liang, Yong, Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate.
  50. Bruel, Michel, Method for heating a wafer by means of a light flux.
  51. Reiley, Timothy Clark; Strand, Timothy Carl, Method for making ohmic contact to silicon structures with low thermal loads.
  52. Masuda, Takashi, Method for manufacturing silicon carbide semiconductor device.
  53. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Method for semiconductor sensor structures with reduced dislocation defect densities.
  54. Malhan,Rajesh Kumar; Takeuchi,Yuichi; Nikitina,Irina; Vassilevski,Konstantin; Wright,Nicholas; Horsfall,Alton, Method of forming an ohmic contact in wide band semiconductor.
  55. Rupp, Roland; Woehlert, Stefan; Gutt, Thomas; Treu, Michael, Method of manufacturing a device by locally heating one or more metalization layers and by means of selective etching.
  56. Rupp, Roland; Woehlert, Stefan; Gutt, Thomas; Treu, Michael, Method of manufacturing a device by locally heating one or more metalization layers and by means of selective etching.
  57. Rupp, Roland; Woehlert, Stefan; Gutt, Thomas; Treu, Michael, Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching.
  58. Endou,Takeshi; Takeuchi,Yuuichi, Method of manufacturing silicon carbide semiconductor device.
  59. Hu, Xiaoming; Craigo, James B.; Droopad, Ravindranath; Edwards, Jr., John L.; Liang, Yong; Wei, Yi; Yu, Zhiyi, Method of removing silicon oxide from a surface of a substrate.
  60. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Methods for semiconductor sensor structures with reduced dislocation defect densities.
  61. Ryu,Sei Hyung; Agarwal,Anant K., Methods of fabricating silicon carbide devices including multiple floating guard ring edge termination.
  62. Ryu, Sei-Hyung; Agarwal, Anant K., Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations.
  63. Ryu, Sei-Hyung; Agarwal, Anant K., Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations.
  64. Mayer, Eric; Alberti, Marc, Methods of forming ohmic layers through ablation capping layers.
  65. Lochtefeld, Anthony J., Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films.
  66. Fiorenza, James; Lochtefeld, Anthony J., Multi-junction solar cells.
  67. Fiorenza, James; Lochtefeld, Anthony J., Multi-junction solar cells.
  68. Ryu,Sei Hyung; Agarwal,Anant K., Multiple floating guard ring edge termination for silicon carbide devices.
  69. Li, Jizhong, Nitride-based multi-junction solar cell modules and methods for making the same.
  70. Li, Jizhong, Nitride-based multi-junction solar cell modules and methods for making the same.
  71. Li, Jizhong; Lochtefeld, Anthony J.; Sheen, Calvin; Cheng, Zhiyuan, Photovoltaics on silicon.
  72. Hydrick, Jennifer M.; Fiorenza, James, Polishing of small composite semiconductor materials.
  73. Hydrick, Jennifer M.; Fiorenza, James, Polishing of small composite semiconductor materials.
  74. Hydrick, Jennifer M.; Fiorenza, James G., Polishing of small composite semiconductor materials.
  75. Cole,Melanie W.; Weihs,Timothy P., Process for nickel silicide Ohmic contacts to n-SiC.
  76. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  77. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  78. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  79. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  80. Cheng, Zhiyuan; Sheen, Calvin, Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures.
  81. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  82. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  83. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  84. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  85. Cheng, Zhiyuan, Reduction of edge effects from aspect ratio trapping.
  86. Biwa, Goshi; Okuyama, Hiroyuki, Selective growth method, and semiconductor light emitting device and fabrication method thereof.
  87. Biwa, Goshi; Okuyama, Hiroyuki, Selective growth method, and semiconductor light emitting device and fabrication method thereof.
  88. Biwa,Goshi; Okuyama,Hiroyuki, Selective growth method, and semiconductor light emitting device and fabrication method thereof.
  89. Wood,Dustin P.; Mallik,Debendra, Selective plating of package terminals.
  90. Wood,Dustin P.; Mallik,Debendra, Selective plating of package terminals.
  91. Eisenbeiser,Kurt; Wang,Jun; Droopad,Ravindranath, Semiconductor device and method.
  92. Tamaso, Hideto, Semiconductor device and method of manufacturing the same.
  93. Nakazawa, Haruo; Tachioka, Masaaki; Fujishima, Naoto; Ogino, Masaaki; Nakajima, Tsunehiro; Iguchi, Kenichi, Semiconductor device manufacturing method.
  94. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  95. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  96. Lochtefeld, Anthony J., Semiconductor diodes fabricated by aspect ratio trapping with coalesced films.
  97. Okuyama,Hiroyuki; Biwa,Goshi, Semiconductor light emitting device and fabrication method thereof.
  98. Suzuki, Jun; Okuyama, Hiroyuki; Biwa, Goshi; Morita, Etsuo, Semiconductor light emitting device and fabrication method thereof.
  99. Cheng, Zhiyuan; Fiorenza, James G.; Sheen, Calvin; Lochtefeld, Anthony, Semiconductor sensor structures with reduced dislocation defect densities.
  100. Cheng, Zhiyuan; Fiorenza, James; Sheen, Calvin; Lochtefeld, Anthony J., Semiconductor sensor structures with reduced dislocation defect densities.
  101. Yu,Zhiyi; Droopad,Ravindranath, Semiconductor structure exhibiting reduced leakage current and method of fabricating same.
  102. Ramdani,Jamal; Droopad,Ravindranath; Hilt,Lyndee L.; Eisenbeiser,Kurt Williamson, Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same.
  103. Thei, Kong-Beng; Yu, Jiun-Lei Jerry; Tsai, Chun Lin; Tuan, Hsiao-Chin; Kalnitsky, Alex, SiC crystalline on Si substrates to allow integration of GaN and Si electronics.
  104. Ryu, Sei-Hyung; Agarwal, Anant K., Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection.
  105. Ramdani,Jamal; Hilt,Lyndee L., Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate.
  106. Emrick, Rudy M.; Bosco, Bruce Allen; Holmes, John E.; Franson, Steven James; Rockwell, Stephen Kent, Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same.
  107. Eisenbeiser, Kurt W.; Yu, Zhiyi; Droopad, Ravindranath, Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same.
  108. Holm, Paige M.; Barenburg, Barbara Foley; Yamamoto, Joyce K.; Richard, Fred V., Structure and method for fabricating semiconductor microresonator devices.
  109. Lempkowski,Robert; Chason,Marc, Structure and method for fabricating semiconductor structures and devices for detecting an object.
  110. Tungare,Aroon; Klosowiak,Tomasz L., Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials.
  111. Krutko, Oleh; Xie, Kezhou; Shokrani, Mohsen; Gupta, Aditya; Gedzberg, Boris, Structures and methods for fabricating vertically integrated HBT-FET device.
  112. Quick, Nathaniel R; Murray, Michael C, Thermal doping of materials.

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