초록 ▼

A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a

A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC. The OPWC is configured in conjunction with the selected signal from the multiplexer, to cause the GC and the latch circuit to generate output pulses having a predetermined pulse width equal to .delta., triggered by the rising edges of the selected signal. Because the second input signal is inverted, during the second mode the output pulses are in effect triggered by the falling edges of the second input signal.

대표청구항 ▼

[ I claim:] [1.] A timing circuit for generating an output pulse triggered by an input pulse of an input signal, the input pulse having a leading edge and a trailing edge, a first signal or a second signal serving as the input signal, the timing circuit comprising:a multiplexer having a first input

[ I claim:] [1.] A timing circuit for generating an output pulse triggered by an input pulse of an input signal, the input pulse having a leading edge and a trailing edge, a first signal or a second signal serving as the input signal, the timing circuit comprising:a multiplexer having a first input lead coupled to receive the first signal and having a second input lead coupled to receive the second signal and having a third input lead coupled to receive a mode signal, wherein the multiplexer is configured to output a selected signal dependent on the first or second signal as a function of a logic level of the mode signal;a first node coupled to receive the selected signal outputted by the multiplexer;a second node;a logic circuit coupled to the third input lead and the first and second nodes, wherein the logic circuit is configured to cause a level at the second node to have a first logic level in response to the leading edge of the input pulse and the logic level of the mode signal and to transition to a second logic level after a predetermined delay period started in response to the trailing edge of the input pulse and the logic level of the mode signal; anda gating circuit having a first input lead, a second input lead and an output lead, the first and second input leads of the gating circuit being respectively coupled to the first and second nodes, wherein the gating circuit is configured to change a voltage level at the output lead of the gating circuit as a function of the logic levels at the first and second nodes; anda latch circuit coupled to the output lead of the gating circuit, the latch circuit being configured to generate the output signal as a function of the voltage level at the output lead of the gating circuit.