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Molded array integrated circuit package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0927704 (1997-09-10)
발명자 / 주소
  • Chia Chok J.
  • Lim Seng-Sooi
  • Low Qwai H.
출원인 / 주소
  • LSI Logic Corp.
인용정보 피인용 횟수 : 36  인용 특허 : 10

초록

One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conduct

대표청구항

[ What is claimed is:] [1.] A semiconductor substrate comprising:a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces;a die attach area on the first surface of the package subs

이 특허에 인용된 특허 (10)

  1. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Ball grid array with via interconnection.
  2. Yoo Youn Cheol (Seoul KRX) Yoo Hee Yeoul (Seoul KRX) Lee Jeong (Joongyang-Ku KRX) Park Doo Hyun (Young Dung Po-Ku KRX) Han In Gyu (Seoul KRX), Chip mounting plate construction of lead frame for semiconductor package.
  3. Exposito Juan,FRX, Injection molded ball grid array casing.
  4. Chakravorty Kishore Kumar,SGX ; Lim Thiam Beng,SGX, Method for forming a highly reliable and planar ball grid array package.
  5. Komathu Kathuzi (Kawagoe JPX), Method of molding a protective cover on a pin grid array.
  6. Low Qwai H. ; Thavarajah Manickam ; Chia Chok J. ; Alagaratnam Maniam, Molded laminate package with integral mold gate.
  7. Variot Patrick (San Jose CA) Chia Chok J. (Campbell CA), Overmolded semiconductor package.
  8. Miyajima Kenji,JPX, Semiconductor apparatus, fabrication method therefor and board frame.
  9. Fukushima Takashi (Osaka JPX) Ito Satoshi (Osaka JPX) Kuwamura Makoto (Osaka JPX) Akizuki Shinya (Osaka JPX) Ikemura Kazuhiro (Osaka JPX) Sudo Shinichiro (Osaka JPX), Semiconductor device.
  10. Aoki Kazumasa,JPX ; Sota Yoshiki,JPX, Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process t.

이 특허를 인용한 특허 (36)

  1. Rumsey, Brad D.; Bolken, Todd O.; Baerlocher, Cary J., Apparatus for reduced flash encapsulation of microelectronic devices.
  2. Bolken,Todd O.; Cobbley,Chad A., Ball grid array packages with thermally conductive containers.
  3. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Circuit and substrate encapsulation methods.
  4. Akihisa Iguchi JP, Circuit board frame and method of use thereof for manufacturing semiconductor device.
  5. Drussel, Zane; Hinkle, Derek, Circuit board singulation methods.
  6. Weggen, Martin Herman; Teunissen, Michel Hendrikus Lambertus; Gal, Wilhelmus Gerardus Jozef, Device and method for encapsulating with encapsulating material and electronic component fixed on a carrier.
  7. Jeng Jacob,TWX ; Chen Kun-Luh,TWX ; Chen Edward,TWX, Integrated circuit package architecture with a variable dispensed compound and method of manufacturing the same.
  8. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  9. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  10. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  11. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  12. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  13. Brad D. Rumsey ; Todd O. Bolken ; Cary J. Baerlocher, Method and apparatus for reduced flash encapsulation of microelectronic devices.
  14. Rumsey, Brad D.; Bolken, Todd O.; Baerlocher, Cary J., Method and apparatus for reduced flash encapsulation of microelectronic devices.
  15. Mercado, Humberto Quezada, Method and system for integrated circuit packaging.
  16. Ahmad, Syed Sajid, Method of Interconnecting substrates for electrical coupling of microelectronic components.
  17. Cobbley,Chad A., Method of encapsulating interconnecting units in packaged microelectronic devices.
  18. Cobbley,Chad A., Method of encapsulating packaged microelectronic devices with a barrier.
  19. Chun Hung Lin TW, Method of molding semiconductor device and molding die for use therein.
  20. Bolken, Todd O., Microelectronic devices and microelectronic die packages.
  21. Wang,Kuang Yu; Ni,Jim; Hsueh,Paul; Chiou,Ren Kang, Molded memory card production using carrier strip.
  22. Shih-Chang Lee TW; Gwo Liang Weng TW, Molding apparatus and molding method for flexible substrate based package.
  23. Kao-Yu Hsu TW; Chun Hung Lin TW; Tao-Yu Chen TW, Molding method for BGA semiconductor chip package.
  24. Cobbley, Chad A., Packaged microelectronic devices with interconnecting units.
  25. James, Stephen L.; Cobbley, Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  26. James,Stephen L.; Cobbley,Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  27. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
  28. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
  29. Ho,Shu Chuen; Liu,Jie; Ong,See Yap, Sectional molding system.
  30. Hashimoto,Nobuaki, Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus.
  31. Shivkumar, Bharat; Cheah, Chuan, Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance.
  32. Drussel Zane ; Hinkle Derek, Singulation methods and substrates for use with same.
  33. Drussel, Zane; Hinkle, Derek, Singulation methods and substrates for use with same.
  34. Shinma, Yasuhiro, Split-mold and method for manufacturing semiconductor device by using the same.
  35. Yasuhiro Shinma JP, Split-mold and method for manufacturing semiconductor device by using the same.
  36. Farnworth, Warren M., Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece.
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