초록 ▼

A bias stabilization circuit for biasing the DC gate bias of a stabilized transistor is disclosed. The bias stabilization circuit may be comprised of a bias transistor that is fabricated concurrent with, and on the same chip as, the stabilized transistor. Preferably, the bias transistor and the stab

A bias stabilization circuit for biasing the DC gate bias of a stabilized transistor is disclosed. The bias stabilization circuit may be comprised of a bias transistor that is fabricated concurrent with, and on the same chip as, the stabilized transistor. Preferably, the bias transistor and the stabilized transistor are fabricated physically close to each other and during the same process so that the electrical characteristics of the transistors are closely related. In a preferred embodiment, a drain of the bias transistor is connected to a load comprising a first resistor, a second resistor, and a third resistor. The drain of the bias transistor is connected through the third resistor to a junction between the first and second resistors. The first and second resistors are connected in series between a first supply potential and a reference potential. The gate and source of the bias transistor are connected together through a fourth resistor. The gate is also connected to a second supply potential that is derived from the first supply potential. The third and fourth resistors are fabricated together with the bias and stabilized transistors. By this configuration, if the operating characteristics of the stabilized transistor varies from chip to chip during fabrication due to process variations, or the supply potentials vary, the bias transistor will compensate to maintain a substantially constant operating point of the stabilized transistor.

대표청구항 ▼

[ What is claimed is:] [1.] A bias stabilization circuit for stabilizing an operating point of a first transistor, said bias stabilization circuit comprising:a second transistor having a gate, a source and a drain, wherein said source is configured to be connected through a first resistor to a first

[ What is claimed is:] [1.] A bias stabilization circuit for stabilizing an operating point of a first transistor, said bias stabilization circuit comprising:a second transistor having a gate, a source and a drain, wherein said source is configured to be connected through a first resistor to a first supply potential, said gate is configured to be connected directly to said first supply potential, and said drain is configured to be connected through a resistive load network to a second supply potential;wherein said drain of said second transistor outputs a bias voltage to the gate of said first transistor, to which it is coupled, such that if there is a change in said operating point of said first transistor, said bias stabilization circuit will automatically adjust said bias voltage to cause said first transistor to return to its original operating point, andwherein said change in said operating point may be caused by variations in said first transistor, said first resistor, said resistive load network, or said first and second spply potentials.