초록 ▼

A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information

A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information item is formed of two bytes, the DMA controller, while temporarily storing data received in odd-numbered order in a data-set adjusting register, controls block write of this together with data received in even-numbered order to the RAM. Due to this, access where data other than these data sets is intermixed is eliminated, even in a case where asynchronous word-unit access of the RAM is performed by the CPU.

대표청구항 ▼

[ What is claimed is:] [1.] A DMA control apparatus for transferring data between memories associated with two different asynchronously operating processors in a data set where one information item is formed by a plurality of data bytes bit-serially communicated in a predetermined byte pattern which

[ What is claimed is:] [1.] A DMA control apparatus for transferring data between memories associated with two different asynchronously operating processors in a data set where one information item is formed by a plurality of data bytes bit-serially communicated in a predetermined byte pattern which includes data transmission commands to a memory, said apparatus comprising:a data-set adjusting register into which a number of data bits making up said data set minus one said bit-serially communicated data byte, are temporarily loaded; andcontrolling means for block-accessing said memory with said data set including data loaded into said data-set adjusting register and said one bit-serially communicated data byte.