$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface u 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
  • G06F-011/00
  • G01R-031/28
출원번호 US-0035490 (1998-03-05)
발명자 / 주소
  • Douskey Steven Michael
  • Cogswell Michael Charles
  • Currier Guy Richard
  • Elliott John Robert
  • Vincent Sharon Denos
  • Wallin James Maurice
  • Wiltgen Paul Leonard
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Stinebruner
인용정보 피인용 횟수 : 188  인용 특허 : 12

초록

A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through

대표청구항

[ What is claimed is:] [1.] An integrated circuit device, comprising:(a) a plurality of cores disposed on the integrated circuit device;(b) a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit devi

이 특허에 인용된 특허 (12)

  1. Rajski Janusz ; Tyszer Jerzy,PLX, Arithmetic built-in self test of multiple scan-based integrated circuits.
  2. Champlin Cary Richard, Boundary-scan testable system and method.
  3. Baird Brian R. ; Richter David E. ; Thusoo Shalesh ; Stark David M. ; Blomgren James S., Debug and video queue for multi-processor chip.
  4. Chang Yi-Hua E. (Poughkeepsie NY) Gruodis Algirdas J. (Wappingers Falls NY) Muhlfeld ; Jr. Hans P. (Highland NY) Rodriguez Charles W. (Bethel CT) Shulman Mark L. (Hyde Park NY), Distributed pattern generator.
  5. Handly Paul Robert ; Deitrich Brian Lee ; Yockey Robert Francis, Hierarchically managed boundary-scan testable module and method.
  6. Mizokawa Takashi,JPX ; Hirayama Katsuhiro,JPX, Integrated circuit and test method therefor.
  7. Nadeau-Dostie Benoit,CAX ; Cote Jean-Francois,CAX, Method and apparatus for high-speed interconnect testing.
  8. Huang Jen-Hsun (San Jose CA) Rostoker Michael D. (San Jose CA) Gluss David (Woodside CA), Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC.
  9. Battaline Robert P. ; Robinson James R. ; Welbon Edward H. ; Williams Ralph J., Performance monitoring through JTAG 1149.1 interface.
  10. Adham Saman M. I. (Kanata CAX), Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths.
  11. Whetsel Lee D., Semiconductor wafer with interconnect between dies for testing and a process of testing.
  12. Cherichetti Cory Ansel ; Colyer Peter Stewart ; Stauffer David Robert, Test mode matrix circuit for an embedded microprocessor core.

이 특허를 인용한 특허 (188)

  1. Whetsel, Lee D., Addressable tap address, state monitor, decode and TMS gating circuitry.
  2. McGowan, Robert A., Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores.
  3. McGowan, Robert A., Apparatus and method for coupling a plurality of test access ports to external test and debug facility.
  4. McGowan, Robert A., Apparatus and method for test and debug of a processor/core having advanced power management.
  5. McGowan, Robert A., Apparatus and method for test and debug of a processor/core having advanced power management.
  6. Azimi, Saeed; Ho, Son, Apparatus and method for testing and debugging an integrated circuit.
  7. Azimi, Saeed; Ho, Son Hong; Smathers, Daniel, Apparatus and method for testing and debugging an integrated circuit.
  8. Azimi, Saeed; Ho, Son; Smathers, Daniel, Apparatus and method for testing and debugging an integrated circuit.
  9. Azimi, Saeed; Ho, Son; Smathers, Daniel, Apparatus and method for testing and debugging an integrated circuit.
  10. Azimi, Saeed; Ho, Son; Smathers, Daniel, Apparatus and method for testing and debugging an integrated circuit.
  11. Azimi, Saeed; Ho, Son; Smathers, Daniel, Apparatus and method for testing and debugging an integrated circuit.
  12. Azimi,Saeed; Ho,Son, Apparatus and method for testing and debugging an integrated circuit.
  13. Azimi,Saeed; Ho,Son; Smathers,Daniel, Apparatus and method for testing and debugging an integrated circuit.
  14. Azimi,Saeed; Ho,Son; Smathers,Daniel, Apparatus and method for testing and debugging an integrated circuit.
  15. Azimi,Saeed; Ho,Son; Smathers,Daniel, Apparatus and method for testing and debugging an integrated circuit.
  16. Douskey, Steven Michael; Hamilton, Michael John; Schenck, Brandon Edward, Asynchronous communication apparatus using JTAG test data registers.
  17. Kohno, Kazuyoshi; Uetani, Hironori, Automatic test vector generation method, test method making use of the test vectors as automatically generated, chip manufacturing method and automatic test vector generation program.
  18. Kanter, Ofir; Peleg, Eran; Levy, Yesayahu, BIST to provide phase interpolator data and associated methods of operation.
  19. Vaglica, John J.; Chun, Christopher K. Y.; Corleto Mena, Jose G.; Cruz, Arnaldo R.; Tao, Jianping; Vu, Mieu V.; Elledge, Mark E.; Khawand, Charbel; Goldberg, Arthur M.; Hayes, David J., Cellular modem processing.
  20. Vaglica, John J.; Chun, Christopher K. Y.; Corleto-Mena, Jose G.; Cruz, Arnaldo R.; Tao, Jianping; Vu, Mieu V.; Elledge, Mark E.; Khawand, Charbel; Goldberg, Arthur M.; Hayes, David J., Cellular modem processing.
  21. Vaglica, John J.; Chun, Christopher K. Y.; Corleto-Mena, Jose G.; Cruz, Arnaldo R.; Tao, Jianping; Vu, Mieu V.; Elledge, Mark E.; Khawand, Charbel; Goldberg, Arthur M.; Hayes, David J., Cellular modem processing.
  22. Hsu,Yu Chin; Tsai,Furshing; Liu,Tayung, Circuit property verification system.
  23. Jones,Michael F.; Giral,Frederick; Fritzsche,William A., Circuit testing with ring-connected test instrument modules.
  24. Jones,Michael F.; Giral,Frederic; Fritzsche,William A., Circuit testing with ring-connected test instruments modules.
  25. Iwashita, Hiroaki, Clock domain crossing verification support.
  26. Wang, Laung-Terng; Hsu, Po-Ching; Wen, Xiaqing, Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults.
  27. Wang,Laung Terng; Hsu,Po Ching; Wen,Xiaoqing, Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults.
  28. Whetsel,Lee D., Connection of auxiliary circuitry to tap and instruction register controls.
  29. Nakatani, Hiroshi; Sameda, Yoshito; Sawada, Akira; Takehara, Jun; Takene, Kouichi; Nishikawa, Hiroyuki, Control apparatus.
  30. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation.
  31. Wang, Yuanlong; Ware, Frederick A., Controller device with retransmission upon error.
  32. Wang, Yuanlong; Ware, Frederick A., Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link.
  33. Wang, Yuanlong; Ware, Frederick A., Controller that receives a cyclic redundancy check (CRC) code from an electrically erasable programmable memory device.
  34. Watanabe,Tomofumi; Suzuki,Takayuki, Data processor.
  35. Watanabe,Tomofumi; Suzuki,Takayuki, Data processor with serial transfer of control program.
  36. Whetsel, Lee D., Data register control of TDI/AX1 to the data register.
  37. Roth,Charles P.; Singh,Ravi P.; Kolagotla,Ravi; Dinh,Tien, Data synchronization for a test access port.
  38. Whetsel, Lee D., Direct scan access JTAG.
  39. Ware, Frederick A.; Perego, Richard E., Dynamic memory supporting simultaneous refresh and data-access transactions.
  40. Ware, Frederick A.; Perego, Richard E., Dynamic memory supporting simultaneous refresh and data-access transactions.
  41. Ware,Frederick A.; Perego,Richard E., Dynamic memory supporting simultaneous refresh and data-access transactions.
  42. Liu, Zhi G.; Nguyen, Megan P.; On, Bill N.; Yong, Suksoon, Dynamic multi-purpose external access points connected to core interfaces within a system on chip (SOC).
  43. Hwang,Bar Chung; Lu,Hsieh Yi, Easy access port structure and access method.
  44. Wang, Yuanlong; Ware, Frederick A., Electrically erasable programmable memory device that generates a cyclic redundancy check (CRC) code.
  45. Wang, Yuanlong; Ware, Frederick A., Electrically erasable programmable memory device that generates error-detection information.
  46. Lai,Benny W. H., Embedded testing capability for integrated serializer/deserializers.
  47. Kessler, Richard E.; Bannon, Peter J.; Gharachorloo, Kourosh; Verghese, Thukalan V., Fault containment and error recovery in a scalable multiprocessor.
  48. Kessler,Richard E.; Bannon,Peter J.; Gharachorloo,Kourosh; Verghese,Thukalan V., Fault containment and error recovery in a scalable multiprocessor.
  49. James W. Meyer, Functional level configuration of input-output test circuitry.
  50. Harris, Scott C., Guaranteed core access in a multiple core processing system.
  51. Mowry, Anthony C.; Farber, David G.; Austin, Michael J.; Moore, John E., Heat management using power management information.
  52. Lee D. Whetsel, Hierarchical access of test access ports in embedded core integrated circuits.
  53. Dervisoglu, Bulent; Cooke, Laurence H., Hierarchical test circuit structure for chips with multiple circuit blocks.
  54. Dervisoglu, Bulent; Cooke, Laurence H., Hierarchical test circuit structure for chips with multiple circuit blocks.
  55. Dervisoglu, Bulent; Cooke, Laurence H., Hierarchical test circuit structure for chips with multiple circuit blocks.
  56. Dervisoglu,Bulent; Cooke,Laurence H., Hierarchical test circuit structure for chips with multiple circuit blocks.
  57. Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Sasaki,Paul T.; Freidin,Philip M.; Asuncion,Santiago G.; Costello,Philip D.; Vadi,Vasisht M.; Bekele,Adebabay M.; Verma,Hare K., High speed configurable transceiver architecture.
  58. Whetsel, Lee D., IC TAP with address, state monitor, and state decode circuitry.
  59. Whetsel, Lee D., IC cores, scan paths, compare circuitry, select and enable inputs.
  60. Whetsel, Lee D., IC with addressable test port.
  61. Kamei,Tatsuya; Nishimoto,Junichi; Tatezawa,Ken, IC with internal interface switch for testability.
  62. Whetsel, Lee D., IC with shared scan cells selectively connected in scan path.
  63. Schulz, Jurgen M., Integrated circuit having distributed control and status registers and associated signal routing means.
  64. Watkins, Daniel R.; Donahue, Hunter S.; Ziaja, Thomas Alan, Integrated circuit with embedded test functionality.
  65. Whetsel, Lee D., Integrated circuits carrying intellectual property cores and test ports.
  66. Vijayaraghavan, Divya; Zheng, Michael Menghui; Lee, Chong H.; Xue, Ning; Nguyen, Tam, Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device.
  67. Gallup,Kendra J.; Matthews,James Albert, Integrated optics and electronics.
  68. Jones, Anthony Mark; Wasson, Paul M.; White, Edmund H., Interactive debug system for multiprocessor array.
  69. McCallops, John A.; Ashbaugh, Kurt E.; Souls, Douglas E., Interchangeable pistol grip handles for pneumatic tools and seals therefor.
  70. De Angeli,Marco; Dang,Loc Thi Xuan; Dupree,Gregory; Gianella,Roberto; Hamilton,Thomas; Lowe,Steven; Portinari,Marco, JTAG and boundary scan automatic chain selection.
  71. Whetsel, Lee D., JTAG multiplexer with clock/mode input, mode/clock input and mode output.
  72. Whetsel, Lee D., JTAG multiplexer with clock/mode input, mode/clock input, and clock output.
  73. Engel, Christopher John; James, Norman Karl; Monwai, Brian Chan; Reick, Kevin F.; Shephard, III, Philip George; Zamora, Marco, JTAG-based software to perform cumulative array repair.
  74. Kanter, Ofir; Peleg, Eran; Shoor, Ehud; Sterin, Eli, Jitter tolerance testing apparatus, systems, and methods.
  75. Cismas, Sorin C; Garbacea, Ilie, Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel.
  76. Cismas, Sorin C; Garbacea, Ilie, Matrix processor data switch routing systems and methods.
  77. Cismas, Sorin C; Garbacea, Ilie, Matrix processor initialization systems and methods.
  78. Cismas, Sorin C.; Garbacea, Ilie, Matrix processor proxy systems and methods.
  79. Cismas, Sorin C; Garbacea, Ilie, Matrix processor proxy systems and methods.
  80. Gaskins,Darius D.; Lundberg,James R., Mechanism for providing measured power management transitions in a microprocessor.
  81. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory chip with error detection and retry modes of operation.
  82. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory controller with error detection and retry modes of operation.
  83. Wang, Yuanlong; Ware, Frederick A., Memory device with retransmission upon error.
  84. Wang, Yuanlong; Ware, Frederick A., Memory device with unidirectional cyclic redundancy check (CRC) code transfer for both read and write data transmitted via bidirectional data link.
  85. Shaeffer, Ian; Hampel, Craig E., Memory error detection.
  86. Shaeffer, Ian; Hampel, Craig E., Memory error detection.
  87. Shaeffer, Ian; Hampel, Craig E., Memory error detection.
  88. Shaeffer, Ian; Hampel, Craig E., Memory error detection.
  89. Shaeffer, Ian; Hampel, Craig E., Memory error detection.
  90. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory system with error detection and retry modes of operation.
  91. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory system with error detection and retry modes of operation.
  92. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory system with error detection and retry modes of operation.
  93. Tsern, Ely K.; Horowitz, Mark A.; Ware, Frederick A., Memory system with error detection and retry modes of operation.
  94. Jahagirdar, Sanjeev; George, Varghese; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor.
  95. Jahagirdar, Sanjeev; George, Varghese; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor.
  96. Jahagirdar, Sanjeev; George, Varghese; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor.
  97. Allarey, Jose; Jahagirdar, Sanjeev, Method and apparatus for a zero voltage processor sleep state.
  98. Allarey, Jose; Jahagirdar, Sanjeev, Method and apparatus for a zero voltage processor sleep state.
  99. Jahagirdar, Sanjeev; George, Varghese; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor sleep state.
  100. Jahagirdar, Sanjeev; George, Varghese; Conrad, John; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor sleep state.
  101. Jahagirdar, Sanjeev; George, Varghese; Conrad, John; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor sleep state.
  102. Jahagirdar, Sanjeev; Varghese, George; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Navch, Alon; Rotem, Shai, Method and apparatus for a zero voltage processor sleep state.
  103. Moyer, William C.; Bruce, William C., Method and apparatus for affecting a portion of an integrated circuit.
  104. Moyer,William C.; Bruce, Jr.,William C., Method and apparatus for affecting a portion of an integrated circuit.
  105. Drerup, Bernard Charles; Nicholas, Richard; Srinivasan, Prasanna, Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining.
  106. Hetrick, William A.; Stover, Jeremy Dean; Tiemeyer, Matt, Method and apparatus for debugging protocol traffic between devices in integrated subsystems.
  107. Weber,Wolf Dietrich; Chou,Chien Chun; Ebert,Jeffrey Allen; Hamilton,Stephen W.; Meyer,Michael J., Method and apparatus for error handling in networks.
  108. Bright,Arthur A.; Crumley,Paul G.; Dombrowa,Marc B.; Douskey,Steven M.; Haring,Rudolf A.; Oakland,Steven F.; Ouellette,Michael R.; Strissel,Scott A., Method and apparatus for in-system redundant array repair on integrated circuits.
  109. Bright,Arthur A.; Crumley,Paul G.; Dombrowa,Marc B.; Douskey,Steven M.; Haring,Rudolf A.; Oakland,Steven F.; Ouellette,Michael R.; Strissel,Scott A., Method and apparatus for in-system redundant array repair on integrated circuits.
  110. Bright,Arthur A.; Crumley,Paul G.; Dombrowa,Marc B.; Douskey,Steven M.; Haring,Rudolf A.; Oakland,Steven F.; Ouellette,Michael R.; Strissel,Scott A., Method and apparatus for in-system redundant array repair on integrated circuits.
  111. Jahagirdar, Sanjeev; George, Varghese; Conrad, John B.; Milstrey, Robert; Fischer, Stephen A.; Naveh, Alon; Rotem, Shai, Method and apparatus for powered off processor core mode.
  112. Floyd,Michael Stephen, Method and apparatus for sending thread-execution-state-sensitive supervisory commands to a simultaneous multi-threaded (SMT) processor.
  113. Arimilli, Ravi Kumar; Reick, Kevin F., Method and apparatus for servicing a processing system through a test port.
  114. Chatterjee, Abhijit; Majernik, Dave; Cherubal, Sasikumar; Chakrabarti, Sudip; Voorakaranam, Ramakrishna; Abraham, Jacob A.; Goodman, Douglas, Method and apparatus for testing a system-on-a-chip.
  115. Mueller, Bernd; Aue, Axel, Method and device for testing a computer core in a processor having at least two computer cores.
  116. Devins, Robert J.; Milton, David W.; Nsame, Pascal A., Method and system of coherent design verification of inter-cluster interactions.
  117. Devins, Robert J.; Milton, David W.; Nsame, Pascal A., Method and system of communicating between peer processors in SoC environment.
  118. Devins, Robert J.; Milton, David W.; Nsame, Pascal A., Method and system of design verification.
  119. Lin,Chih Wen, Method for functional verification of hardware design.
  120. Nadeau-Dostie, Benoit; Côté, Jean-François, Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same.
  121. Jenkins, IV,Jesse H., Methods and circuits for realizing a performance monitor for a processor from programmable logic.
  122. Wang, Laung-Terng; Hsu, Po-Ching; Wen, Xiaoqing, Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test.
  123. Wang, Laung-Terng; Hsu, Po-Ching; Wen, Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test.
  124. Wang, Laung-Terng; Hsu, Po-Ching; Wen, Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test.
  125. Wang, Laung-Terng; Hsu, Po-Ching; Wen, Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test.
  126. Wang,Laung Terng; Hsu,Po Ching; Wen,Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test.
  127. Wang, Laung-Terng; Hsu, Po-Ching; Kao, Shih-Chia; Lin, Meng-Chyi; Wang, Hsin-Po; Chao, Hao-Jan; Wen, Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test.
  128. Wang, Laung-Terng; Hsu, Po-Ching; Kao, Shih-Chia; Lin, Meng-Chyi; Wang, Hsin-Po; Chao, Hao-Jan; Wen, Xiaqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test.
  129. Wang, Laung-Terng; Hsu, Po-Ching; Kao, Shih-Chia; Lin, Meng-Chyi; Wang, Hsin-Po; Chao, Hao-Jan; Wen, Xiaqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test.
  130. Wang,Laung Terng (L. T.); Hsu,Po Ching; Kao,Shih Chia; Lin,Meng Chyi; Wang,Hsin Po; Chao,Hao Jan; Wen,Xiaoqing, Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test.
  131. Wang, Laung-Terng (L.-T.); Lin, Meng-Chyi; Wen, Xiaoqing; Wang, Hsin-Po; Hsu, Chi-Chan; Kao, Shih-Chia; Hsu, Fei-Sheng, Multiple-capture DFT system for scan-based integrated circuits.
  132. Wang,Laung Terng; Wen,Xiaoqing, Multiple-capture DFT system for scan-based integrated circuits.
  133. Wang, Laung-Terng; Chao, Hao-Jan; Wu, Shianling, Multiple-capture DFT system to reduce peak capture power during self-test or scan test.
  134. Wang, Laung-Terng; Wu, Shianling; Jiang, Zhigang; Liu, Jinsong; Chao, Hao-Jan; Yu, Lizhen; Zhao, Feifei; Li, Fangfang; Yan, Jianping, Multiple-capture DFT system to reduce peak capture power during self-test or scan test.
  135. Shivaray, Banadappa V; Chauhan, Pranjal; Surathkal, Pramod; Warshofsky, Alex S.; Knopp, Tomai; Bhowmick, Soumitra Kumar; Ansari, Ahmad R., Non-destructive online testing for safety critical applications.
  136. Bhavsar Dilip Kantilal ; Gowan Michael Karl, Observability register architecture for efficient production test and debug.
  137. Kimelman,Paul; Field,Ian, On-board diagnostic circuit for an integrated circuit.
  138. Gallup, Kendra; Baugh, Brenton A.; Wilson, Robert E.; Matthews, James A.; Coleman, Christopher L.; Snyder, Tanya J.; Williams, James H., Optical device package with turning mirror and alignment post.
  139. Ford, Simon Andrew; Reid, Alastair David; Kneebone, Katherine Elizabeth; Grimley-Evans, Edmund, Performing diagnostic operations upon an asymmetric multiprocessor apparatus.
  140. McCallops, John A.; Ashbaugh, Kurt E.; Hamlin, Mark J.; Heinrichs, Kevin; Souls, Douglas E., Pneumatic tool housings having embedded electronic devices.
  141. Naveh, Alon; Rotem, Efraim; Weissmann, Eliezer, Power management coordination in multi-core processors.
  142. Olivier Garreau, Programmable JTAG network architecture to support proprietary debug protocol.
  143. Whetsel, Lee D., Receiving addresses on moving TLR to R/TI when TDI high.
  144. Crowell, Daniel M.; Kitamorn, Alongkorn; Reick, Kevin F.; Tran, Thi N., Recovery from hardware access errors.
  145. Whetsel, Lee D., Reduced power testing with equally divided scan paths.
  146. Lippett, Mark David, Resource management in a multicore architecture.
  147. Lippett, Mark David, Resource management in a multicore architecture.
  148. Whetsel, Lee D., Scan circuit low power adapter with counter.
  149. Whetsel, Lee D., Scan paths with gating, enable, and select decode control circuits.
  150. Whetsel,Lee D.; Haroun,Baher S.; Lasher,Brian J.; Kinra,Anjali, Selecting different 1149.1 TAP domains from update-IR state.
  151. Moyer, William C.; Gumulja, Jimmy, Selective MISR data accumulation during exception processing.
  152. Andersen, John E.; Cowan, Bruce M.; Gillis, Pamela S.; Oakland, Steven F.; Ouellette, Michael R., Self test method and device for dynamic voltage screen functionality improvement.
  153. Perner, Frederick A.; Eldredge, Kenneth J.; Tran, Lung, Self-testing of magneto-resistive memory arrays.
  154. Matsuda,Genichiro; Shimamura,Akimitsu; Fukatsu,Gen, Semiconductor apparatus.
  155. Iizuka, Yoshikazu, Semiconductor apparatus and testing method.
  156. Morita,Akira, Semiconductor device and method for controlling the same.
  157. Kurita,Yuji; Yamashita,Hiroyoshi; Nishiwaki,Hitoaki, Semiconductor device with mechanism for leak defect detection.
  158. Koki Noguchi JP, Semiconductor integrated circuit and recording medium.
  159. Miura, Takashi; Miyamori, Takashi, Semiconductor integrated circuit, system board and debugging system.
  160. Tanizaki, Tetsushi; Hamamoto, Takeshi, Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification.
  161. Volz, Aaron Matthew; Vandivier, Suzette Denise; Slavick, Jeffrey Andrew, Serializer/de-serializer bus controller interface.
  162. Azimi, Saeed; Ho, Son Hong; Smathers, Daniel, Serializer/deserializer and method for transferring data between an integrated circuit and a test interface.
  163. Songer,Christopher M.; Newlin,John; Nuggehalli,Srikanth; Jacobowitz,David Glen, Simultaneous real-time trace and debug for multiple processing core systems on a chip.
  164. Liu, Zhiwu, Soft coding of multiple device IDs for IEEE compliant JTAG devices.
  165. McHale,David F; Varma,Rahoul K; Wicks,Marc R; Livesley,Mike; Duncan,Gareth, Storage of trace data within a data processing apparatus.
  166. Bueti, Serafino; Goodnow, Kenneth J.; Leonard, Todd E.; Mann, Gregory J.; Woodruff, Charles S., Structure for task based debugger (transaction-event-job-trigger).
  167. Gallup,Kendra; Baugh,Brenton A.; Wilson,Robert E.; Matthews,James A.; Williams,James H.; Wang,Tak Kui, Surface emitting laser package having integrated optical element and alignment post.
  168. Duncan,Richard L., Synchronizer apparatus for synchronizing data from one clock domain to another clock domain.
  169. Azimi, Saeed; Ho, Son Hong; Smathers, Daniel, System and method for providing a test result from an integrated to an analyzer.
  170. Azimi, Saeed; Ho, Son; Smathers, Daniel, System and method for testing an integrated circuit embedded in a system on a chip.
  171. Pelley, Perry H., System and method for testing and providing an integrated circuit having multiple modules or submodules.
  172. Azimi, Saeed; Ho, Son Hong; Smathers, Daniel, System and method for transferring serialized test result data from a system on a chip.
  173. Wang, Yuanlong; Ware, Frederick A., System and module comprising an electrically erasable programmable memory chip.
  174. Whetsel, Lee D., TAP and AUX with IR control of TDI input multiplexer.
  175. Whetsel, Lee D., TAP and auxiliary circuitry with auxiliary output multiplexer and buffers.
  176. Whetsel, Lee D., Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O.
  177. Whetsel, Lee D., Tap and auxiliary circuitry with auxiliary output multiplexer and buffers.
  178. Whetsel, Lee D., Tap with address, state monitor and gating circuitry.
  179. Bueti, Serafino; Goodnow, Kenneth J.; Leonard, Todd E.; Mann, Gregory J.; Woodruff, Charles S., Task based debugger (transaction-event-job-trigger).
  180. Swamy, Janardhana, Techniques for testing embedded cores in multi-core integrated circuit designs.
  181. Miner, David E.; Tu, Steven J.; Murray, Scott W., Test access port.
  182. Miner, David E.; Tu, Steven J.; Murray, Scott W., Test access port.
  183. Miner,David E.; Tu,Steven J.; Murray,Scott W., Test access port.
  184. Song, Won-Hyung, Test board having a plurality of test modules and a test system having the same.
  185. Goff, Lonnie C., Test circuit topology reconfiguration and utilization techniques.
  186. Lerner, Abner, Test system having a master/slave JTAG controller.
  187. Whetsel, Lee D., Tester, parallel scan paths, and comparators in same functional circuits.
  188. Gallup,Kendra J.; Geefay,Frank S.; Fazzio,Ronald Shane; Johnson,Martha; Guthrie,Carrie Ann; Snyder,Tanya Jegeris; Ruby,Richard C., Wafer-level packaging of optoelectronic devices.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로