초록 ▼

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

대표청구항 ▼

[ What is claimed:] [1.] A system comprising:a component receiving a reference clock and including a clock generator to generate an internal clock running at a first frequency; anda controller to generate a clock frequency change indication and to place the component into a low activity state,the cl

[ What is claimed:] [1.] A system comprising:a component receiving a reference clock and including a clock generator to generate an internal clock running at a first frequency; anda controller to generate a clock frequency change indication and to place the component into a low activity state,the clock generator having a setting changed in response to the clock frequency change indication to change the frequency of the internal clock to a second frequency while the component is in the low activity state,the clock generator at a first setting providing the internal clock at the first frequency based on the reference clock, and the clock generator at a second setting providing the internal clock at the second frequency based on the same reference clock.