초록 ▼

It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory a

It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started. The newly requested direct memory access, which has been kept waiting, is started when any direct memory access which has already been carried out finishes, and enough capacity is free in the common bus for carrying out the newly requested direct memory access.

대표청구항 ▼

[ What is claimed is:] [1.] A data transfer control method, for controlling direct memory access performed by direct memory access controllers in a system including processors, said direct memory access controllers, which are connected with a common bus, comprising steps of:a) determining, when star

[ What is claimed is:] [1.] A data transfer control method, for controlling direct memory access performed by direct memory access controllers in a system including processors, said direct memory access controllers, which are connected with a common bus, comprising steps of:a) determining, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using said bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all said processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing said memory, and a latency for bus-right arbitration;b) starting the newly requested direct memory access when said step a) determines that the direct memory access can be started;c) keeping starting of the newly requested direct memory access waiting when said step a) determines that the direct memory access cannot be started; andd) starting the newly requested direct memory access, which has been kept waiting by said step c), when any direct memory access which has already been carried out finishes, and enough capacity is free in said common bus for carrying out the newly requested direct memory access.