초록 ▼

A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plu

A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.

대표청구항 ▼

[ What is claimed is:] [1.] An apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system, comprising:a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory;a pl

[ What is claimed is:] [1.] An apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system, comprising:a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory;a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory;a first level arbiter coupled to the plurality of slow data port interfaces configured to choose an access request of one the slow data ports and output the access request; anda second level arbiter coupled to the plurality of fast data port interfaces and to the output of the first level arbiter configured to choose an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter to be serviced by the buffer memory.