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On-chip bus architecture that is both processor independent and scalable 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0062363 (1998-04-17)
발명자 / 주소
  • Nannetti Gianni Michele,GBX
  • Parvataneni Tirumal Rao,GBX
출원인 / 주소
  • Mentor Graphics Corporation
대리인 / 주소
    Blakely Sokoloff Taylor & Zafman, LLP
인용정보 피인용 횟수 : 148  인용 특허 : 5

초록

A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus inter

대표청구항

[ What is claimed is:] [1.] An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a slave function block also coupled to the bus, the first bus master function block having a bus master interface including a state machine that conducts a bus transaction be

이 특허에 인용된 특허 (5)

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  5. Singhal Ashok ; Liencres Bjorn ; Price Jeff ; Cerauskis Frederick M. ; Broniarczyk David ; Cheung Gerald ; Hagersten Erik ; Agarwal Nalini, Split transaction snooping bus protocol.

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