초록 ▼

Ultra high-speed multi-level interconnect structure and fabrication process flows are disclosed for a semiconductor integrated circuit chip. The interconnect structures of this invention include a plurality of electrically conductive metallization levels. Each of the metallization levels includes a

Ultra high-speed multi-level interconnect structure and fabrication process flows are disclosed for a semiconductor integrated circuit chip. The interconnect structures of this invention include a plurality of electrically conductive metallization levels. Each of the metallization levels includes a plurality of electrically conductive interconnect lines. A plurality of electrically conductive plugs make electrical connections between various metallization levels as well as between the metallization levels and the semiconductor devices fabricated on the semiconductor substrate. The invention further includes a free-space medium occupying at least a substantial fraction of the electrically insulating regions within the multi-level interconnect structure surrounding the interconnect lines and plugs. A top passivation overlayer hermetically seals the multi-level interconnect structure. The top passivation overlayer used for hermetic sealing also functions as a heat transfer medium to facilitate heat removal from the interconnect metallization structure as well as to provide additional mechanical support for the multi-level interconnect structure through contact with the top metallization level of the multi-level interconnect structure. The hermetically sealed free-space medium minimizes the capacitive cross-talk noise in the interconnect structure, enabling increased chip operating speeds and reduced chip power distribution.

대표청구항 ▼

[ What is claimed is:] [1.] A method for formation of a multi-level interconnect structure comprising the steps of:fabricating a plurality of metallization levels comprising a plurality of electrically conductive interconnect segments, said metallization levels separated by and embedded within a dis

[ What is claimed is:] [1.] A method for formation of a multi-level interconnect structure comprising the steps of:fabricating a plurality of metallization levels comprising a plurality of electrically conductive interconnect segments, said metallization levels separated by and embedded within a disposable interlevel and inter-metal material layers;fabricating a plurality of electrically conductive plugs in conjunction with said metallization levels and embedded within said disposable interlevel and inter-metal material layers;depositing a top insulator layer over said plurality of metallization levels;forming a plurality of openings within said top insulating layer;selectively removing said disposable inter-level and inter-metal material layers to form a free-space dielectric medium surrounding at least a substantial portion of said plurality of metallization levels and said electrically a conductive plugs;forming a hermetically-sealed interconnect structure with a free-space dielectric medium by depositing an electrically insulating material layer and sealing said plurality of openings without substantially shrinking the overall volume of said free-space dielectric medium; andforming the bonding pad openings.