초록 ▼

A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability

A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an input signal is applied to the gate of the transistor P1, a precharge signal is applied to the gate of the transistor N1, an inverted signal of the precharge signal is applied to the gate of the transistor P2, the gate of the transistor N2 is connected to an intermediate node A, an input signal S.sub.IN is input to each delay element as the precharge signal, and when the input signal S.sub.IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S.sub.IN is sequentially propagated by delay elements, and thus a delay signal is obtained.

대표청구항 ▼

[ What is claimed is:] [1.] A delay circuit for outputting an input signal taking a first or a second level delayed by exactly a predetermined time,said delay circuit having:a first holding means for receiving a control signal and holding a first node at a first level in accordance with the control

[ What is claimed is:] [1.] A delay circuit for outputting an input signal taking a first or a second level delayed by exactly a predetermined time,said delay circuit having:a first holding means for receiving a control signal and holding a first node at a first level in accordance with the control signal;a second holding means for holding a second node at a second level in accordance with a second control signal;a first switching means for receiving the input signal and switching the first node from the first level to the second level when the input signal switches from the second level to the first level; anda second switching means for switching the second node from the second level to the first level in accordance with a level change of the first node and outputting the signal of the second node.