[특허]Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture

[미국특허] Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-029/00
출원번호	US-0009445 (1998-01-20)
발명자 / 주소	Bolam Ronald J. Kulkarni Subhash B. Schepis Dominic J.
출원인 / 주소	International Business Machines Corporation
대리인 / 주소	Ratner & PrestiaAbate
인용정보	피인용 횟수 : 30 인용 특허 : 12

초록 ▼

An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

대표청구항 ▼

[ What is claimed is:] [1.] A silicon-on-insulator semiconductor chip comprising:a peripheral edge;a substrate;an oxide layer on the substrate;a silicon layer on the oxide layer;a passivation layer on the silicon layer;an active area including a gate deposited above the silicon layer, a gate metal contact deposited above and forming an electrical contact with the gate, and at least one metal contact deposited above and forming an electrical contact with the silicon layer;an isolation barrier including a groove:(a) being disposed slightly inward of the peripheral edge of the chip,(b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and(c) surrounding completely the active area of the chip; anda barrier material deposited (i) over the passivation layer on the silicon layer, and (ii) in the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.

이 특허에 인용된 특허 (12) 인용/피인용 타임라인 분석

Linn Jack H. (Melbourne FL) Lowry Robert K. (Melbourne Beach FL) Rouse George V. (Indiatlantic FL) Buller James F. (Austin TX) Speece William H. (Palm Bay FL), Bonded wafer processing.
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Ning Tak H. (Yorktown Heights NY) Wu Ben S. (Yorktown Heights NY), FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures.
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Lynch William T. (Summit NJ) Parrillo Louis C. (Warren NJ), Method for fabricating CMOS devices.
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Ishikawa Tamotsu (Yokohama JPX) Tanaka Hirokazu (Kawasaki JPX) Tabata Akira (Zama JPX), Method for fabricating a dielectric isolated integrated circuit device.
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Bajor George (Melbourne FL) Rivoli Anthony L. (Palm Bay FL), Method for forming recessed oxide isolation containing deep and shallow trenches.
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Kawamura Akio (Nara JPX), Method for forming semiconductor device isolating regions.
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Solomon Allen L. (Fullerton CA), Process for making a double wafer moated signal processor.
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Tashiro Tsutomu (Tokyo JPX), Semiconductor device.
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Usui Shouji (Tokyo JPX) Inagaki Taketoshi (Kawasaki JPX) Kamei Kiyomasa (Tokyo JPX) Matsutani Takeshi (Machida JPX) Imaoka Kazunori (Komae JPX), Semiconductor device having SOI substrate and fabrication method thereof.
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Usui Shouji (Tokyo JPX) Inagaki Taketoshi (Kawasaki JPX) Kamei Kiyomasa (Tokyo JPX) Matsutani Takeshi (Machida JPX) Imaoka Kazunori (Komae JPX), Semiconductor device having a SOI substrate and fabrication method thereof.
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Suzawa Hideomi,JPX, Semiconductor device including active matrix circuit.
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Delgado Jose A. (Palm Bay FL) Gaul Stephen J. (Melbourne FL) Rouse George V. (Indialantic FL) McLachlan Craig J. (Melbourne Beach FL), Ultra-thin circuit fabrication by controlled wafer debonding.
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이 특허를 인용한 특허 (30) 인용/피인용 타임라인 분석

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Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Shahidi, Ghavam G., Field effect transistor devices with dopant free channels and back gates.
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Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Shahidi, Ghavam G., Field effect transistor devices with dopant free channels and back gates.
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Dong-Hyuk Ju, Heat removal by removal of buried oxide in isolation areas.
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Warwick, Andrew M., Insulated-gate field-effect semiconductor device.
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Basker, Veeraraghavan S.; Cheng, Kangguo; Doris, Bruce B.; Hook, Terence B.; Khakifirooz, Ali; Kerber, Pranita; Yamashita, Tenko; Yeh, Chun-Chen, Integrated circuit including DRAM and SRAM/logic.
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Basker, Veeraraghavan S.; Cheng, Kangguo; Doris, Bruce B.; Hook, Terence B.; Khakifirooz, Ali; Kulkarni, Pranita; Yamashita, Tenko; Yeh, Chun-Chen, Integrated circuit including DRAM and SRAM/logic.
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Olson, Michael L.; Dalebout, William T., Magnetic resistance mechanism in a cable machine.
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Takahashi, Akira, Method for forming semiconductor device.
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Takahashi,Akira, Method for forming semiconductor device.
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Beyer, Klaus; Schepis, Dominic, Method of forming shallow trench isolation for thin silicon-on-insulator substrates.
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Dekker, Ronald; Maas, Henricus Godefridus Rafael; Timmering, Cornelis Eustatius; Bancken, Pascal Henri Leon, Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer.
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Ashby, Darren, Post workout massage device.
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Fallica, Piero, Power integrated circuit with vertical current flow and related manufacturing process.
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Assaderaghi, Fariborz; Rausch, Werner; Schepis, Dominic Joseph; Shahidi, Ghavam G., SOI MOSFETS exhibiting reduced floating-body effects.
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Sune, Ching-Tzong, Self-aligned copper plating/CMP process for RF lateral MOS device.
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Schulze, Hans-Joachim; Voss, Stephan; Zundel, Markus, Semiconductor device.
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Morikado, Mutsuo, Semiconductor device and method of manufacturing the same.
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Schulze, Hans-Joachim; Voss, Stephan; Zundel, Markus, Semiconductor device with staggered oxide-filled trenches at edge region.
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Katsumi Abe JP; Kazuhisa Mori JP, Semiconductor support substrate potential fixing structure for SOI semiconductor device.
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Furukawa, Toshiharu; Robison, Robert R.; Williams, Richard Q., Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure.
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Furukawa, Toshiharu; Robison, Robert R.; Williams, Richard Q., Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure.
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Bolam,Ronald J.; Kulkami,Subhash B.; Schepis,Dominic J., Silicon-on-insulator chip having an isolation barrier for reliability.
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Ronald J. Bolam ; Subhash B. Kulkarni ; Dominic J. Schepis, Silicon-on-insulator chip having an isolation barrier for reliability.
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Pei, Chengwen; Wang, Geng, Suppression of diffusion in epitaxial buried plate for deep trenches.
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Brammer, Chase, System and method for controlling an exercise device.
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IPC	Description
A	생활필수품
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A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture 원문보기