$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
출원번호 US-0245958 (1999-02-05)
발명자 / 주소
  • Agahi Farid
  • Bronner Gary
  • Flietner Bertrand
  • Hammerl Erwin,DEX
  • Ho Herbert
  • Srinivasan Radhika
출원인 / 주소
  • Infineon Technologies North America Corp.
대리인 / 주소
    Delio & Peterson, LLCMa
인용정보 피인용 횟수 : 38  인용 특허 : 12

초록 ▼

A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating ox

대표청구항 ▼

[ Thus, having described the invention, what is claimed is:] [16.] A method of reducing current leakage in an isolation trench of a semiconductor device comprising the steps of:(a) providing a silicon wafer having a dielectric layer disposed thereon;(b) etching at least one trench into said wafer;(c

이 특허에 인용된 특허 (12)

  1. Ho Herbert (Washingtonville NY) Hammerl Erwin (Stormville NY) Dobuzinsky David M. (Hopewell Junction NY) Palm J. Herbert (Wappingers Falls NY) Fugardi Stephen (New Milford CT) Ajmera Atul (Wappinger , Application of thin crystalline Si3N4liners in shallow trench isolation (STI) structures.
    상세보기
  2. Galli Carol (Odenton MD) Hsu Louis L. (Fishkill NY) Ogura Seiki (Hopewell Junction NY) Shepard Joseph F. (Hopewell Junction NY), Isolation structure using liquid phase oxide deposition.
    상세보기
  3. Hymes Diane J. ; Ravkin Mikhail ; Krusell Wibur C. ; Noorai Venus, Method and apparatus for cleaning of semiconductor substrates using standard clean 1 (SC1).
    상세보기
  4. Lee Tzung-Han,TWX, Method for removing a top corner of a trench.
    상세보기
  5. Hunter William R. (Garland TX) Slawinski Christopher (Austin TX) Teng Clarence W. (Plano TX), Method of fabricating defect free trench isolation devices.
    상세보기
  6. Okada Daisuke (Koganei JPX) Uchida Akihisa (Koganei JPX) Takakura Toshihiko (Koganei JPX) Nakashima Shinji (Koganei JPX) Ohno Nobuhiko (Tokorozawa JPX) Ogiue Katsumi (Hinode JPX), Method of forming trench isolation in an integrated circuit.
    상세보기
  7. Cooper Kent J. (Austin TX) Roth Scott S. (Austin TX), Method of making a contact structure.
    상세보기
  8. Lee Kuo-Hua (Lehigh County PA) Lu Chih-Yuan (Lehigh County PA), Semiconductor device manufacture including trench formation.
    상세보기
  9. Bose Amitava (Nashua NH) Garver Marion M. (Marlborough MA) Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Shallow trench isolation process for high aspect ratio trenches.
    상세보기
  10. Moon Peter K. ; Landau Berni W. ; Krick David T., Shallow trench isolation technique.
    상세보기
  11. Benedict John Preston ; Dobuzinsky David Mark ; Flaitz Philip Lee ; Hammerl Erwin N.,DEX ; Ho Herbert ; Moseman James F. ; Palm Herbert,DEX ; Yoshida Seiko,JPX ; Takato Hiroshi, Shallow trench isolation with oxide-nitride/oxynitride liner.
    상세보기
  12. Deckert Cheryl A. (Lawrenceville NJ) Schnable George L. (Lansdale PA), Silicon nitride and silicon oxide etchant.
    상세보기

이 특허를 인용한 특허 (38)

  1. Chou, Cheng-Hsien; Chou, Shih Pei; Lai, Chih-Yu; Chen, Sheng-Chau; Chen, Chih-Ta; Tu, Yeur-Luen; Tsai, Chia-Shiung, Deep trench isolation shrinkage method for enhanced device performance.
    상세보기
  2. Chou, Cheng-Hsien; Tseng, Hsiao-Hui; Lai, Chih-Yu; Chou, Shih Pei; Chiang, Yen-Ting; Tsai, Min-Ying, Deep trench isolations and methods of forming the same.
    상세보기
  3. Doris, Bruce B.; Ponoth, Shom; Khare, Prasanna; Liu, Qing; Loubet, Nicolas; Vinet, Maud, Dual shallow trench isolation liner for preventing electrical shorts.
    상세보기
  4. Doris, Bruce B.; Ponoth, Shom; Khare, Prasanna; Liu, Qing; Loubet, Nicolas; Vinet, Maud, Dual shallow trench isolation liner for preventing electrical shorts.
    상세보기
  5. Doris, Bruce B.; Ponoth, Shom; Khare, Prasanna; Liu, Qing; Loubet, Nicolas; Vinet, Maud, Dual shallow trench isolation liner for preventing electrical shorts.
    상세보기
  6. Doris, Bruce B.; Ponoth, Shom; Khare, Prasanna; Liu, Qing; Loubet, Nicolas; Vinet, Maud, Dual shallow trench isolation liner for preventing electrical shorts.
    상세보기
  7. Brodsky, Colin J.; Friedman, Anne C.; Ho, Herbert Lei; Kim, Byeong Yeol; Mocuta, Dan Mihai; Oakley, Garrett W.; Yu, Chienfan, High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control.
    상세보기
  8. Tsai, Cheng-Yuan; Lin, Chih-Lung; Hsueh, Cheng-Chen Calvin, Isolation structures and methods of fabricating isolation structures.
    상세보기
  9. Shinya Ito JP, Method for fabrication semiconductor device having trench isolation structure.
    상세보기
  10. Park, Cheol Hwan; Park, Dong Su; Lee, Tae Hyeok; Woo, Sang Ho, Method for forming device isolation film of semiconductor device.
    상세보기
  11. Chun, In Kyu, Method for forming isolation layer in semiconductor devices.
    상세보기
  12. Kim,Do Hyung; Kim,Sung Eui, Method for forming layer for trench isolation structure.
    상세보기
  13. Won, Jongik, Method for performing a deep trench etch for a planar lightwave circuit.
    상세보기
  14. Kim,Ji young; Kim,Ki nam, Method of fabricating semiconductor device having junction isolation insulating layer.
    상세보기
  15. Kim, Do-Hyung; Kim, Sung-Bong; Hong, Jung-In, Method of forming a device isolation trench in an integrated circuit device.
    상세보기
  16. Akira Mitsuiki JP, Method of forming a shallow trench isolation structure in a semiconductor device.
    상세보기
  17. Hong, Soo-Jin, Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace.
    상세보기
  18. Kumamoto, Keita, Method of forming a trench isolation structure having a second nitride film.
    상세보기
  19. Lou Chine-Gie,TWX, Method of forming shallow trench isolation structure.
    상세보기
  20. Ji, Hua; Kim, Dong Jun; Kim, Jin-Ho; Jang, Chuck, Method of forming trench isolation without grooving.
    상세보기
  21. Chu-Yun Fu TW; Li-Jen Chen TW, Method to reduce STI HDP-CVD USG deposition induced defects.
    상세보기
  22. Sharan, Sujit; Sandhu, Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.
    상세보기
  23. Sharan,Sujit; Sandhu,Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.
    상세보기
  24. Sharan,Sujit; Sandhu,Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.
    상세보기
  25. Derderian,Garo J.; Manning,H. Montgomery, Methods of forming trench isolation regions.
    상세보기
  26. Beintner,Jochen; Divakaruni,Rama; Jammy,Rajarao, Nitrided STI liner oxide for reduced corner device impact on vertical device performance.
    상세보기
  27. Shimizu, Shu, Non-volatile semiconductor memory device and method of manufacturing the same.
    상세보기
  28. Ramkumar, Krishnaswamy; Wong, Kaichiu; Jayatilaka, Venuka, Process for reducing leakage in an integrated circuit with shallow trench isolated active areas.
    상세보기
  29. Codding, Steven Ross; Greco, Joseph R.; Krywanczyk, Timothy Charles, Recycling of ion implantation monitor wafers.
    상세보기
  30. Renegarajan, Rajesh; LaRosa, Giuseppe; Dellow, Mark, Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization.
    상세보기
  31. Lee, Yu Jun; Jang, Kyoung Chul, Semiconductor device and method for forming the same.
    상세보기
  32. Park, Tai-su; Park, Kyung-won; Kim, Sung-jin, Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation.
    상세보기
  33. Lee, Jae-Hwan; Kim, Sangsu; Yang, Changjae, Semiconductor device having fin-type field effect transistor and method of manufacturing the same.
    상세보기
  34. Yun, Eun-Jung; Kim, Sung-Eui, Semiconductor trench isolation structure.
    상세보기
  35. Kim, Sung-eui; Lee, Keum-joo; Hwang, In-seak; Koh, Young-sun; Ahn, Dong-ho; Park, Moon-han; Park, Tai-su, Trench isolation regions having recess-inhibiting layers therein that protect against overetching.
    상세보기
  36. Kim, Do-Hyung; Kim, Sung-Eui, Trench isolation structure.
    상세보기
  37. Ji, Hua; Kim, Dong Jun; Kim, Jin-Ho; Jang, Chuck, Trench isolation without grooving.
    상세보기
  38. Beyer, Klaus D.; O'Neil, Patricia A.; Ryan, Deborah A.; Smeys, Peter; Leobandung, Effendi, Triple oxide fill for trench isolation.
    상세보기

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

저작권 관리 안내

문의처: helpdesk@kisti.re.kr전화: 080-969-4114

Copyright KISTI. All Rights Reserved.

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로