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Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0285998 (1999-04-01)
발명자 / 주소
  • Bogin Zohar
  • Freker David E.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 72  인용 특허 : 9

초록

An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumpt

대표청구항

[ What is claimed is:] [1.] A method for reducing the power-consumption of a system memory comprising a plurality of units of memory components that may independently one from another be placed in a reduced power-consumption state, wherein:a separate clock enable signal is provided to each of said p

이 특허에 인용된 특허 (9)

  1. Wong Keng L. ; Fernando Roshan, Apparatus and a method for embedding dynamic state machines in a static environment.
  2. Hardin Jennefer S. ; Kubick Robert F. ; Langendorf Brian K., Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM.
  3. Iwamura Masahiro,JPX ; Tanaka Shigeya,JPX ; Maejima Hideo,JPX ; Nakano Tetsuo,JPX, Low power consumption semiconductor integrated circuit device and microprocessor.
  4. Ishii Satoki,JPX ; Inoue Yoshitsugu,JPX ; Yamada Masahiro,JPX ; Noro Toru,JPX, Memory system, memory control system and image processing system.
  5. Volk Andrew M. (Loomis CA), Method and apparatus for placing an integrated circuit chip in a reduced power consumption state.
  6. Shiraishi Taketora (Itami JPX) Teraoka Eiichi (Itami JPX) Kengaku Toru (Itami JPX), Microprocessor having built-in synchronous memory with power-saving feature.
  7. Harston Stephen W. (Limerick IEX), Random access memory with apparatus for reducing power consumption.
  8. Tomita Hiroyoshi,JPX, Semiconductor apparatus having a voltage unit and a backup unit for providing a reduced power consumption.
  9. Lawrence Archer R ; Little Jack C, Synchronous memory tester.

이 특허를 인용한 특허 (72)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Woodbridge,Nancy G.; Bibikar,Vasu J., Anticipatory power control of memory.
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Branover, Alexander; Steinman, Maurice B., Cache flush based on idle prediction and probe activity level.
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  21. Kareenhalli,Suryaprasad; Bogin,Zohar B.; Loonawat,Gautam, Cycle type based throttling.
  22. Yajima, Shinji; Fueki, Shunsuke; Nakajima, Masao, Data processing apparatus and card-sized data processing device.
  23. Yoshida, Toyohiko; Yamada, Akira; Sato, Hisakazu, Data processing apparatus of high speed process using memory of low speed and low power consumption.
  24. Worthington, Bruce L.; Sharda, Vishal; Zhang, Qi; Kavalanekar, Swaroop, Dynamic memory allocation and relocation to create low power regions.
  25. Worthington, Bruce L.; Sharda, Vishal; Zhang, Qi; Kavalanekar, Swaroop, Dynamic memory allocation and relocation to create low power regions.
  26. Riesenman, Robert J.; Dodd, James M., Early power-down digital memory device and method.
  27. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  28. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  29. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  30. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  31. Samson, Eric C.; Navale, Aditya; Puffer, David M., Filter based throttling.
  32. Kocev, Andrej; Branover, Alexander, Function based dynamic power control.
  33. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  34. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  39. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  40. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  41. Chen,Sho Mo; Ye,Fei; Yang,Feng, Low power memory sub-system architecture.
  42. Balakrishnan, Kedarnath; Brandl, Kevin M.; Magro, James R., Low power memory throttling.
  43. Jeddeloh, Joe M., Memory device power managers and methods.
  44. Jeddeloh, Joe M., Memory device power managers and methods.
  45. Gooding,Thomas Michael, Memory management to enable memory deep power down mode in general computing systems.
  46. Woodbridge, Nancy G., Memory reuse for multiple endpoints in USB device.
  47. Woodbridge, Nancy G., Memory reuse for multiple endpoints in USB device.
  48. Ma, Kenneth, Method and apparatus for adaptive power management of memory subsystem.
  49. Ma,Kenneth, Method and apparatus for adaptive power management of memory subsystem.
  50. Ma,Kenneth, Method and apparatus for adaptive power management of memory subsystem.
  51. Kaxiras,Stefanos; Diodato,Philip W.; McLellan, Jr.,Hubert Rae; Narlikar,Girija, Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines.
  52. Hu,Zhigang; Kaxiras,Stefanos; Martonosi,Margaret, Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay.
  53. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  54. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  55. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  56. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  58. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  59. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  60. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  61. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  62. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  63. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  64. Takashima,Satoshi; Nishida,Hideshi; Kimura,Kozo; Kiyohara,Tokuzo, Microprocessor.
  65. Branover, Alexander; Steinman, Maurice B.; So, Ming L.; Zheng, Xiao Gang, North-bridge to south-bridge protocol for placing processor in low power state.
  66. David J. Harriman ; David I. Poisner ; Jeff Rabe, Power management method for a computer system having a hub interface architecture.
  67. Bonanno, James J.; Cadigan, Jr., Michael J.; Collura, Adam B.; Lipetz, Daniel; Meaney, Patrick J.; Walters, Craig R., Predictive scheduler for memory rank switching.
  68. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  69. Master,Paul L.; Watson,John, Storage and delivery of device features.
  70. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  71. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  72. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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