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Method of fabricating a stacked via in copper/polyimide beol 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/768
출원번호 US-0936090 (1997-09-23)
발명자 / 주소
  • Cronin John E.
  • Luther Barbara J.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson LLCPeterson
인용정보 피인용 횟수 : 30  인용 특허 : 17

초록

A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insu

대표청구항

[ Thus, having described the invention, what is claimed is:] [1.] A method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect comprising the steps of:a) forming a first interconnect region to which contact is to be made;b) forming a first ins

이 특허에 인용된 특허 (17)

  1. Cronin John E. (Milton VT) Farrar ; Sr. Paul A. (So. Burlington VT) Kaanta Carter W. (Colchester VT) Ryan James G. (Essex Junction VT) Watts Andrew J. (Milton VT), Gray level mask.
  2. Chatterjee Pallab K. (Dallas TX), Integrated circuit with metal interconnecting layers above and below active circuitry.
  3. Chiang Chien ; Pan Chuanbin ; Ochoa Vicky M. ; Fang Sychyi ; Fraser David B. ; Sum Joyce C. ; Ray Gary William ; Theil Jeremy A., Interconnect structure with hard mask and low dielectric constant materials.
  4. Chen Hung-Sheng (San Jose CA) Nguyen Tim (Milpitas CA) Moberly Larry (Santa Clara CA) Teng Chih S. (San Jose CA), Method for forming contact openings in a multi-layer structure that reduces overetching of the top conductive structure.
  5. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  6. Chow Ming-Fea (Poughquagh NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY), Method of forming fine conductive lines, patterns and connectors.
  7. Cederbaum Carl (Paris FRX) Chanclou Roland (Perthes FRX) Combes Myriam (Evry FRX) Mon Patrick (Ponthierry FRX), Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom.
  8. Cederbaum Carl (Paris FRX) Chanclou Roland (Perthess FRX) Combes Myriam (Evry FRX) Mone Patrick (Ponthierry FRX) Vallet Vincent (Mennecy FRX), Method of forming stacked tungsten gate PFET devices and structures resulting therefrom.
  9. Cronin John E. (Milton VT) Farrar ; Sr. Paul A. (Burlington VT) Kaanta Carter W. (Colchester VT) Ryan James G. (Essex Junction VT) Watts Andrew J. (Milton VT), Method of making a gray level mask.
  10. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines.
  11. Matsukawa Naohiro (Kamakura JPX) Nozawa Hiroshi (Yokohama JPX), Method of making high density dielectric isolated gate MOS transistor.
  12. Santadrea Joseph F. (Los Altos Hills CA) Lee Ji-Min (Palo Alto CA) Lien Chuen-Der (Mountain View CA) Huggins Alan H. (Gilroy CA), Parallel manufacturing of semiconductor devices and the resulting structure.
  13. Moslehi Mehrdad M. (Collin County TX) Saraswat Krishna C. (Santa Clara County CA), Planarized multilevel interconnection for integrated circuits.
  14. Cronin John E. (Milton VT) Farrar ; Sr. Paul A. (Burlington VT) Geffken Robert M. (Burlington VT) Guthrie William H. (Essex Junction VT) Kaanta Carter W. (Colchester VT) Previti-Kelly Rosemary A. (Ri, Plural level chip masking.
  15. Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Previti-Kelly Rosemary A. (Richmond VT) Ryan James G. (Essex Junction VT), Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositio.
  16. Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Lee Pei-Ing P. (Williston VT) Previti-Kelly Rosemary A. (Richmond VT) Ryan James G. (Essex Junction VT) Yoon Jung H. (Poughkeepsie NY), Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer composition.
  17. Cochran William T. (New Tripoli PA) Garcia Agustin M. (Allentown PA) Hills Graham W. (Allentown PA) Yeh Jenn L. (Macungie PA), Semiconductor devices having multi-level metal interconnects.

이 특허를 인용한 특허 (30)

  1. Rajagopalan,Nagarajan; Shek,Meiyee; Lee,Albert; Lakshmanan,Annamalai; Xia,Li Qun; Cui,Zhenjiang, Adhesion improvement for low k dielectrics to conductive materials.
  2. Woo, Christy Mei-Chu; Joo, Young-Chang; Lukanc, Todd, Barrier layer integrity test.
  3. Coolbaugh, Douglas D.; Downes, Keith E.; Lindgren, Peter J.; Stamper, Anthony K., Dual-damascene process to fabricate thick wire structure.
  4. Coolbaugh, Douglas D.; Downes, Keith E.; Lindgren, Peter J.; Stamper, Anthony K., Dual-damascene process to fabricate thick wire structure.
  5. Coolbaugh, Douglas D.; Downes, Keith E.; Lindgren, Peter J.; Stamper, Anthony K., Dual-damascene process to fabricate thick wire structure.
  6. Coolbaugh, Douglas D.; Downes, Keith E.; Lindgren, Peter J; Stamper, Anthony K., Dual-damascene process to fabricate thick wire structure.
  7. Ogawa,Kazuto; Inazawa, legal representative,Rie; Hayashi,Hisataka; Ohiwa,Tokuhisa; Inazawa, deceased,Koichiro, Etching method.
  8. Lim,Yeow Kheng; Cha,Randall Cher Liang; See,Alex; Goh,Wang Ling, Integrated circuit with self-aligned line and via and manufacturing method therefor.
  9. Wang, Shi-Qing; Chung, Henry; Lin, James, Integrated circuits with multiple low dielectric-constant inter-metal dielectrics.
  10. Won-Suk Yang KR, Method for fabricating a semiconductor memory device and the structure thereof.
  11. Jang Soon-Kyou,KRX, Method for fabricating contact electrode of the semiconductor device.
  12. Kim, Jong-Doo; Jeon, Joong-Won; Kwon, Young-Deok; Lee, Suk-Joo, Method for fabricating semiconductor device including a via hole in a mask pattern.
  13. Mizoguchi, Takafumi; Shiraishi, Kojiro, Method for manufacturing display device.
  14. Oyamatsu, Hisato, Method for manufacturing multilayer wiring structure semiconductor device.
  15. Mizoguchi, Takafumi; Shiraishi, Kojiro, Method for manufacturing semiconductor device with sidewall.
  16. Inoue, Yushi, Method for producing semiconductor device.
  17. Trivedi,Jigish D., Method of fabricating stacked local interconnect structure.
  18. Assefa, Solomon; Gaidis, Michael C.; Hummel, John P.; Kanakasabapathy, Sivananda K., Method of forming vertical contacts in integrated circuits.
  19. Schneegans, Manfred; Weidgans, Bernhard; Haering, Franziska, Multi-layer metal pads.
  20. Schneegans, Manfred; Weidgans, Bernhard; Haering, Franziska, Multi-layer metal pads.
  21. Welstand, Robert Bernard, On-chip interconnect circuits with use of large-sized copper fill in CMP process.
  22. Huang, Judy H.; Bencher, Christopher Dennis; Rathi, Sudha; Ngai, Christopher S.; Kim, Bok Hoen, Plasma treatment for copper oxide reduction.
  23. Feurprier, Yannick; Lee, Joe; Liebmann, Lars W.; Mignot, Yann; Spooner, Terry A.; Trickett, Douglas M.; Yilmaz, Mehmet, Self aligned via in integrated circuit.
  24. Feurprier, Yannick; Lee, Joe; Liebmann, Lars W.; Mignot, Yann; Spooner, Terry A.; Trickett, Douglas M.; Yilmaz, Mehmet, Self aligned via in integrated circuit.
  25. Huang, Judy H.; Bencher, Christopher Dennis; Rathi, Sudha; Ngai, Christopher S.; Kim, Bok Hoen, Semiconductor device having reduced oxidation interface.
  26. Huang, Judy H.; Bencher, Christopher Dennis; Rathi, Sudha; Ngai, Christopher S.; Kim, Bok Hoen, Semiconductor device having silicon carbide and conductive pathway interface.
  27. Briggs, Benjamin D.; Clevenger, Lawrence A.; DeProspo, Bartlet H.; Huang, Huai; Penny, Christopher J.; Rizzolo, Michael, Skip-vias bypassing a metallization level at minimum pitch.
  28. Briggs, Benjamin D.; Clevenger, Lawrence A.; DeProspo, Bartlet H.; Huang, Huai; Penny, Christopher J.; Rizzolo, Michael, Skip-vias bypassing a metallization level at minimum pitch.
  29. Mizoguchi, Takafumi; Shiraishi, Kojiro; Tsubuku, Masashi, Thin film element, semiconductor device, and method for manufacturing the same.
  30. Mizoguchi, Takafumi; Shiraishi, Kojiro; Tsubuku, Masashi, Thin film element, semiconductor device, and method for manufacturing the same.
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