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Integrated circuit with bonding layer over active circuitry 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
출원번호 US-0959410 (1997-10-28)
발명자 / 주소
  • Shen Chi-Cheong
  • Abbott Donald C.
  • Bucksch Walter,DEX
  • Corsi Marco
  • Efland Taylor Rice
  • Erdeljac John P.
  • Hutter Louis Nicholas
  • Mai Quang
  • Wagensohner Konrad,DEX
  • Williams Charles Edward
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Brady, III
인용정보 피인용 횟수 : 143  인용 특허 : 4

초록

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal

대표청구항

[ What is claimed is:] [1.] An integrated circuit device, comprising:a silicon substrate;an active circuit fabricated in said substrate comprised of electrical components;a metallization layer formed over said active circuit; andan electrically conductive bonding surface positioned directly over sai

이 특허에 인용된 특허 (4)

  1. Steitz Richard R. (Chippewa Falls WI) Christie Diane M. (Eau Claire WI) Neumann Eugene F. (Chippewa Falls WI) August Melvin C. (Chippewa Falls WI) Nelson Stephen (Chippewa Falls WI), Method of fabricating metallized chip carriers from wafer-shaped substrates.
  2. Hsue Chen-Chiu,TWX ; Chien Sun-Chieh,TWX, Polycide bonding pad structure.
  3. DiGiacomo Giulio (Hopewell Junction NY) Kim Jung-Ihl (Seoul NY KRX) Narayan Chandrasekhar (Hopewell Junction NY) Purushothaman Sampath (Yorktown Heights NY), Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal.
  4. Harada Keizo (Itami JPX) Takikawa Takatoshi (Itami JPX) Maeda Takao (Itami JPX) Ban Shunsuke (Itami JPX) Yamanaka Shosaku (Itami JPX), Wiring board having laminated wiring patterns.

이 특허를 인용한 특허 (143)

  1. Doug Baumann ; Louis Pandula, Area efficient bond pad placement.
  2. Hsia, Chin Chiu; Yao, Chih Hsiang; Huang, Tai Chun; Peng, Chih Tang, Bond pad structure for wire bonding.
  3. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  4. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  5. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  6. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  8. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  9. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  10. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
  11. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  12. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  13. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  14. Lin,Mou Shiung, Chip structure with redistribution traces.
  15. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
  16. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  17. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  18. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  23. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  29. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
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  31. Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton , Integrated circuit with bonding layer over active circuitry.
  32. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  33. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  34. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
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  37. Kim, Min-Seok, Metal line in semiconductor device and method for forming the same.
  38. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.
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  41. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  42. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  43. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  44. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  45. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  50. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  52. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with frame support structure.
  53. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with meshed support structure.
  54. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  55. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  56. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  103. Lin, Mou-Shiung, Solder interconnect on IC chip.
  104. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  105. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
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  139. Seshan, Krishna; Singh, Kuljeet, Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method.
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