초록 ▼

A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a printer using the data processing method. In the printer, a CPU bus 70 having a 16-bit physical bus width, is shared by a CPU 21 and a DMAC 80.

A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a printer using the data processing method. In the printer, a CPU bus 70 having a 16-bit physical bus width, is shared by a CPU 21 and a DMAC 80. In a case where the CPU 21 accesses a memory via the CPU bus 70 with an 8-bit width, while the DMAC 80 accesses the memory via the CPU bus 70 with a 16-bit width, each time the DMAC 80 needs to access the memory, the DMAC 80 issues a DMA request signal to the CPU 21, requiring an exclusive access right for the CPU bus 70. In accordance with the request signal, the CPU 21 delivers the exclusive access right for the CPU bus 70 to the DMAC 80. Then the DMAC 80 controls memory access with the 16-bit width.

대표청구항 ▼

[ What is claimed is:] [1.] A data processing method for accessing a memory by a CPU and a DMA controller via a bus with an N-bit physical bus width, comprising:a first access step, of executing a first mode in which said CPU accesses said memory with an N1-bit width:a second access steps of executi

[ What is claimed is:] [1.] A data processing method for accessing a memory by a CPU and a DMA controller via a bus with an N-bit physical bus width, comprising:a first access step, of executing a first mode in which said CPU accesses said memory with an N1-bit width:a second access steps of executing a second mode in which said DMA controller DMA-accesses said memory with an N2-bit width;a detection step, of detecting a request as to whether to execute said first mode or second mode; anda switching steps of, based on the detection in said detection step, switching between execution of said first mode and that of said second mode, such that said CPU or said DMA controller which has an exclusive right for said bus can execute memory access,wherein N, N1 and N2 are respectively positive integers, N2 is greater than N1, and N is equal to or greater than N2.