초록 ▼

A process for the preparation of hermetically sealed electronically active microstructures involves the preparation of a plurality of microstructures and associated conductive paths and lead bond areas on a single wafer such that areas surrounding the microstructures are maintained in a planar condi

A process for the preparation of hermetically sealed electronically active microstructures involves the preparation of a plurality of microstructures and associated conductive paths and lead bond areas on a single wafer such that areas surrounding the microstructures are maintained in a planar condition. A second wafer having a plurality of microstructure-receiving cavities is placed atop the first wafer and fusion or anodically bonded. The microstructures are preferably connected to lead bond pads which lie outside the surround, the second wafer also having bond pad accessing through-holes to facilitate bonding electrical leads to the devices after sawing from the wafer. The lead-connected devices may be further encapsulated by injection molding, potting, or other conventional encapsulative packaging techniques.

대표청구항 ▼

[ What is claimed is:] [1.] A process for the micromachining, and simultaneous encapsulating of a plurality of microstructures fabricated on a single planar silicon wafer, comprising:defining a plurality of fusion bond surround areas on said planar silicon wafer;fabricating a plurality of electronic

[ What is claimed is:] [1.] A process for the micromachining, and simultaneous encapsulating of a plurality of microstructures fabricated on a single planar silicon wafer, comprising:defining a plurality of fusion bond surround areas on said planar silicon wafer;fabricating a plurality of electronically active microstructures within said fusion bond surround areas such that said fusion bond surround areas are maintained in a substantially mutual co-planar condition;providing electrical communication between electronically active portions of said microstructures and a plurality of microstructure-associated lead bond pads exterior to said fusion bond surround areas surrounding said microstructures by fabricating a plurality of conductive pathways between said microstructures and said associated bond pads through said fusion bond surround areas by doping portions of said fusion bond surround areas with a dopant material such that the conductive pathways are flush with the fusion bond surround;positioning an encapsulating wafer on said planar silicon wafer, portions of said encapsulating wafer contacting said fusion bond surround areas;directly bonding said planar and encapsulating wafers to form a bond along said fusion bond surround areas and between said wafers, such that said microstructures are located in cavities defined between surfaces on said planar silicon wafer and said encapsulating wafer.