초록 ▼

An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal

An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

대표청구항 ▼

[ What is claimed is:] [1.] An input block for an integrated circuit (IC), the input block comprising:a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition;b) a control terminal adapted to receive a delay instruction from a

[ What is claimed is:] [1.] An input block for an integrated circuit (IC), the input block comprising:a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition;b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal, the variable signal source progressively changing the delay instruction such that the delay period progressively changes;c) a variable delay circuit having:an input node connected to the input terminal;an output node;at least one delay element for providing a delayed version of the input signal on the output node; anda control node adapted to receive the delay instruction from the control terminal, rein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; andd) a monitor element whereby the delayed version of the input signal on the output node is monitored for a metastable condition.