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Metallized interconnection structure and method of making the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0090380 (1998-06-04)
발명자 / 주소
  • Cheung Robin W.
  • Ting Chiu H.
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 42  인용 특허 : 11

초록

A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been

대표청구항

[ What is claimed is:] [1.] A method of forming a layered conductive structure in a semiconductor device, comprising the steps of:forming an opening in a first insulating layer consisting of a self-copper diffusion barrier material;depositing a seed layer on the first insulating layer;patterning a r

이 특허에 인용된 특허 (11)

  1. Avanzino Steven ; Gupta Subhash ; Klein Rich ; Luning Scott D. ; Lin Ming-Ren, Dual damascene with a sacrificial via fill.
  2. Hong Sam-Hyo,SEX, Electromigration resistant metallization structures for microcircuit interconnections with RF-reactively sputtered titan.
  3. Shimoto Tadanori,JPX ; Funada Yoshitsugu,JPX ; Matsui Koji,JPX ; Shimada Yuzo,JPX ; Utsumi Kazuaki,JPX, Interconnection structures and method of making same.
  4. Shipley ; Jr. Charles R. (Newton MA), Method for manufacture of multilayer circuit board.
  5. Havemann Robert H. (Garland TX), Method of fabricating a self-aligned contact using organic dielectric materials.
  6. Chang Kenneth (Hopewell Junction NY) Czornyj George (Poughkeepsie NY) Farooq Mukta S. (Hopewell Junction NY) Kumar Ananda H. (Hopewell Junction NY) Pitler Marvin S. (late of Poughkeepsie NY by Peter , Method of making a multilayer thin film structure.
  7. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  8. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance.
  9. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  10. Poris Jaime (409 Capitola Ave. Capitola CA 95010), Selective metal electrodeposition process.
  11. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.

이 특허를 인용한 특허 (42)

  1. Barth, Hans-Joachim, Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys.
  2. Mayer Steven T. ; Contolini Robert J., Electroplanarization of large and small damascene features using diffusion barriers and electropolishing.
  3. Lin, Chun Chieh; Su, Hung-Wen; Tsai, Minghsing; Jang, Syun-Ming, Gap filling method for dual damascene process.
  4. Eaves, David M.; Zeng, Xiang; Hennig, Kelly J.; Chang-Chien, Patty Pei-Ling, Hermetic circuit ring for BCB WSA circuits.
  5. Mayer, Steven T.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation.
  6. Mayer, Steven T.; Contolini, Robert J.; Broadbent, Eliot K.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation.
  7. Reid, Jonathan David, Method for electrochemical planarization of metal surfaces.
  8. Morrow, Patrick, Method for making a dual damascene interconnect using a dual hard mask.
  9. J. Neal Cox, Method for making integrated circuits.
  10. Kunieda, Masatoshi; Okumura, Takafumi, Method for manufacturing printed wiring board and printed wiring board.
  11. Mayer,Steven T.; Reid,Jonathan D.; Rea,Mark L.; Emesh,Ismail T.; Meinhold,Henner W.; Drewery,John S., Method for planar electroplating.
  12. Iijima, Makoto; Nukiwa, Masaru; Ueno, Seiji; Morioka, Muneharu, Method of forming an insulative substrate having conductive filled vias.
  13. Niuya, Takayuki; Ono, Michihiro; Goto, Hideto, Method of manufacturing semiconductor device and manufacturing apparatus.
  14. Sergey Lopatin ; Richard J. Huang, Method of re-working copper damascene wafers.
  15. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  16. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  17. Parikh, Suketu A., Misalignment tolerant techniques for dual damascene fabrication.
  18. Mayer, Steven T.; Porter, David W., Modulated metal removal using localized wet etching.
  19. Katz, Anne T., Reducing layer separation and cracking in semiconductor devices.
  20. Mayer, Steven T.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  21. Mayer, Steven T.; Drewery, John; Hill, Richard S.; Archer, Timothy; Kepten, Avishai, Selective electrochemical accelerator removal.
  22. Mayer, Steven T.; Stowell, Marshall R.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  23. Lin, Chun-Chieh; Su, Hung-Wen; Tsai, Ming-Hsing; Jang, Syun-Ming, Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components.
  24. Lin, Chun-Chieh; Su, Hung-Wen; Tsai, Ming-Hsing; Jang, Syun-Ming, Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components.
  25. Cheung,Robin W.; Sinha,Ashok K., Semiconductor device interconnect fabricating techniques.
  26. Kriz, Jakob; Urbansky, Norbert, Semiconductor structure and method for making same.
  27. Meinhold, Dirk; Dallmann, Gerald; Vater, Alfred, Semiconductor structure and method for making same.
  28. Dallmann, Gerald; Rosslau, Heike; Urbansky, Norbert; Wallace, Scott, Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  39. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  40. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  41. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
  42. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
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