초록 ▼

In a motion vector detection apparatus, cascade-connected processor elements each calculates the absolute value of the difference between each of a plurality of pixels which compose a picture and a corresponding one of the same number of pixels included in a block, and also performs cumulative addit

In a motion vector detection apparatus, cascade-connected processor elements each calculates the absolute value of the difference between each of a plurality of pixels which compose a picture and a corresponding one of the same number of pixels included in a block, and also performs cumulative addition of the difference absolute values in the block. These operations are performed for each of the blocks within the predetermined search area. A comparative device repeatedly compares the cumulative addition values of two blocks obtained sequentially in the processor element at the final stage, and selects the smaller one of the cumulative addition values. A subtracter compares the smaller cumulative addition value with a setting value. When the smaller cumulative addition value is smaller than the setting value, a control circuit halts the supply of clock signals to the processor elements and the comparison device, so as to halt the entire operations of the apparatus. Consequently, the power consumption can be reduced.

대표청구항 ▼

[ What is claimed is:] [1.] A motion vector detection apparatus for detecting correlation between a picture consisting of a plurality of pixels and a plurality of blocks each consisting of a same number of pixels as said picture, the plurality of blocks being included within a predetermined search a

[ What is claimed is:] [1.] A motion vector detection apparatus for detecting correlation between a picture consisting of a plurality of pixels and a plurality of blocks each consisting of a same number of pixels as said picture, the plurality of blocks being included within a predetermined search area containing a larger number of pixels than said picture, said motion vector detection apparatus comprising:a plurality of processor elements which are cascade-connected, each of said plurality of processor elements calculating a difference absolute value between each of the plurality of pixels included in said picture and a corresponding one of pixels included in every one of the plurality of blocks, and performing cumulative addition of the difference absolute values for every one of the plurality of blocks sequentially;a comparison means for repeatedly comparing cumulative addition values of the difference absolute values of two of the plurality of blocks by subtraction, the cumulative addition values being obtained in a processor element at a final stage, and for repeatedly selecting a smaller cumulative addition value; anda restriction means for placing restrictions on calculation of at least one of said comparison means and said plurality of processor elements, so as to give a cumulative addition value finally obtained in said comparison means a possibility of becoming a sufficiently small cumulative addition value even if the cumulative addition value is not smallest.