초록 ▼

A novel ESD protection circuit for multiple power supplies, having both inventive inter-rail ESD circuitry and inventive single-rail ESD circuitry. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for

A novel ESD protection circuit for multiple power supplies, having both inventive inter-rail ESD circuitry and inventive single-rail ESD circuitry. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for a diode string is set by the number of diodes within the diode string and preferably a sufficient number of diodes are provided within each diode string for power-up and power-down sequence independence. The single-rail ESD circuitry is connected to a level-shifter and may comprise an RC discriminator comprising two NFET transistors connected in series. The RC discriminator may be connected to a clamping transistor via a buffering circuit, such as an inverter stage, that isolates the gate capacitance of the clamping transistor from the RC discriminator so that the RC characteristics of the RC discriminator are unaffected by the choice of the clamping transistor. The ESD protection circuit may be constructed from a selection from user-selectable discrete circuit elements formed on the chip.

대표청구항 ▼

[ What is claimed is:] [1.] A structure comprising:a first power rail;a second power rail;a third power rail;a first single-rail Electrostatic-Discharge (ESD) protection circuit connected between the first power rail and the third power rail;a second single-rail ESD protection circuit connected betw

[ What is claimed is:] [1.] A structure comprising:a first power rail;a second power rail;a third power rail;a first single-rail Electrostatic-Discharge (ESD) protection circuit connected between the first power rail and the third power rail;a second single-rail ESD protection circuit connected between the second power rail and the third power rail comprising a level-shifter;a first series of diodes connected between the first power rail and the second power rail; anda second series of diodes connected between the level-shifter of the second single-rail ESD protection circuit and the first power rail and having a polarity orientation opposite to the first series of diodes;wherein the level shifter and the first series and second series of diodes are arranged between said first and second power rails to provide power-up sequence independence or power-down sequence independence between said first and second power rails.