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Clock signal from an adjustable oscillator for an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-008/00
출원번호 US-0348532 (1999-07-07)
발명자 / 주소
  • Norman Robert D.
  • Chevallier Christophe J.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lunderberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 91  인용 특허 : 26

초록

An integrated circuit is described which has circuitry to detect environmental conditions such as temperature and supply voltage and adjust the operation of the circuit accordingly. A flash memory system is described which includes a temperature detector and a supply voltage detector. The memory mon

대표청구항

[ What is claimed is:] [1.] A ring oscillator circuit comprising:a first inverting circuit and a plurality of succeeding inverting circuits coupled together in a ring, each inverting circuit having an input and an output, an input of each succeeding inverting circuit being coupled to an output of a

이 특허에 인용된 특허 (26)

  1. Manning Troy A. (Boise ID), Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM.
  2. Landgraf Marc E. (Folsom CA) Javanifard Jahanshir J. (Sacramento CA) Winston Mark D. (El Dorado Hills CA), Circuitry for power supply voltage detection and system lockout for a nonvolatile memory.
  3. Bailey Joseph A. (Austin TX), Clock control technique and system for a microprocessor including a thermal sensor.
  4. Norman Robert D. ; Chevallier Christophe J., Clock signal from an adjustable oscillator for an integrated circuit.
  5. Keeth Brent (Boise ID), Control circuit responsive to its supply voltage level.
  6. Manning Troy A. (Boise ID), Controlling dynamic memory refresh cycle time.
  7. Tillinghast Charles W. (Boise ID) Cohen Michael S. (Boise ID) Voshell Thomas W. (Boise ID), Dynamic RAM array for emulating a static RAM array.
  8. Tobita Youichi (Hyogo JPX), Dynamic random access memory having a plurality of rated voltages as operation supply voltage and operating method there.
  9. Chern Wen-Foo (Boise ID), High efficiency charge pump.
  10. Schutz Joseph D. (Portland OR) Rash Bill C. (Saratoga CA), Integrated circuit device that selects its own supply voltage by controlling a power supply.
  11. Pascucci Luigi (Sesto San Giovanni ITX) Olivo Marco (Bergamo ITX) Golla Carla Maris (Sesto San Giovanni ITX), Internal timing method and circuit for programmable memories.
  12. Wojciechowski Kenneth E. (Folsom CA), Low current reduced area programming voltage detector for flash memory.
  13. Irrinki V. Swamy ; Kapoor Ashok ; Leung Raymond ; Owens Alex ; Wik Thomas R., Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array.
  14. Ware Frederick A. (Los Altos Hills CA) Gasbarro James A. (Mountain Vew CA) Dillon John B. (Palo Alto CA) Farmwald Michael P. (Portola Valley CA) Horowitz Mark A. (Palo Alto CA) Griffin Matthew M. (Mo, Method and apparatus for implementing refresh in a synchronous DRAM system.
  15. Jungroth Owen (Sonora CA) Price Thomas C. (Fair Oaks CA), Nonvolatile memory with automatic power supply configuration.
  16. Chevallier Christophe J. (Palo Alto CA) Roohparvar Frankie F. (Cupertino CA) Briner Michael S. (San Jose CA), Power level detection circuit.
  17. Dhong Sang H. (Mahopac NY) Shin Hyun J. (Mahopac NY) Hwang Wei (Armonk NY), Power supply tracking regulator for a memory array.
  18. Keeth Brent (Boise ID), Ring oscillator enable circuit with immediate shutdown.
  19. Jeong Dong Sik (Kyoungki-do KRX), Self-refresh period adjustment circuit for semiconductor memory device.
  20. Furuno Takeshi (Kodaira JPX) Nakamura Yasuhiro (Kodaira JPX) Matsuo Akinori (Higashiyamato JPX), Semiconductor integrated circuit operable and programmable at multiple voltage levels.
  21. Yoo Seung-Moon (Suwon KRX) Haq Ejaz ul (Seoul KRX) Choi Yun-Ho (Suwon KRX) Cho Soo-In (Seoul KRX) Chin Dae-Je (Seoul KRX) Kang Nam-Soo (Suwon KRX) Lee Seung-Hun (Suwon KRX), Semiconductor memory device.
  22. Ono Yoshitaka (Kawasaki JPX), Semiconductor memory device with refresh timer circuit.
  23. Inagaki Yasaburo (Tokyo JPX), Semiconductor memory device with variable self-refresh cycle.
  24. Blodgett Greg A., Temperature sensitive oscillator circuit.
  25. Tillinghast Charles W. (Boise ID) Cohen Michael S. (Boise ID) Voshell Thomas W. (Boise ID), Temperature-dependent DRAM refresh circuit.
  26. Casper Stephen L. (Boise ID) Loughmiller Daniel R. (Boise ID), Voltage compensating delay element.

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  2. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
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  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Crispin,Thomas A., Apparatus and method for reducing sequential bit correlation in a random number generator.
  7. Michael J. Dunn ; Mark Brandon Fuselier, Apparatus and method for verifying process integrity.
  8. Chen, Chi-Yang; Huang, San-Yueh, Calibration circuit for voltage regulator.
  9. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  10. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  11. Altmejd,Morrie, Computer system and method of using temperature measurement readings to detect user activity and to adjust processor performance.
  12. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  13. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  14. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  15. Suda, Masakatsu; Sudou, Satoshi, Consumption current balance circuit, compensation current amount adjusting method, timing generator, and semiconductor testing apparatus.
  16. Zhang,Fulong; Scholz,Harold D., Digital I/O timing control.
  17. Drexler, Adrian J., Dual-phase delay-locked loop circuit and method.
  18. Drexler, Adrian J., Dual-phase delay-locked loop circuit and method.
  19. Walker, Robert Michael, Dynamic control of memory access speed.
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  21. Huber, Brian W., Fast accessing of a memory device using decoded address during setup time.
  22. Thomann Mark R. ; Lee Terry R., High speed I/O calibration using an input path and simplified logic.
  23. Masleid, Robert P, Inverting zipper repeater circuit.
  24. Masleid, Robert P., Inverting zipper repeater circuit.
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  26. Masleid, Robert, Leakage efficient anti-glitch filter.
  27. Garlepp, Bruno Werner; Chau, Pak Shing; Donnelly, Kevin S.; Portmann, Clemenz; Stark, Donald C.; Sidiropoulos, Stefanos; Barth, Richard M.; Davis, Paul G.; Tsern, Ely K., Method and apparatus for adjusting the performance of a synchronous memory system.
  28. Garlepp,Bruno Werner; Chau,Pak Shing; Donnelly,Kevin S.; Portmann,Clemenz; Stark,Donald C.; Sidiropoulos,Stefanos; Barth,Richard M.; Davis,Paul G.; Tsern,Ely K., Method and apparatus for adjusting the performance of a synchronous memory system.
  29. Kurd, Nasser A.; Barkatullah, Javed S., Method and apparatus for detecting on-die voltage variations.
  30. Kurd,Nasser A.; Barkatullah,Javed S., Method and apparatus for detecting on-die voltage variations.
  31. Guliani, Sandeep K.; Sundaram, Rajesh; Rao, Hari M.; Javanifard, Johnny, Method and apparatus for flash voltage detection and lockout.
  32. Guliani, Sandeep K.; Sundaram, Rajesh; Rao, Hari M.; Javanifard, Johnny, Method and apparatus for flash voltage detection and lockout.
  33. Luick,David Arnold, Method and apparatus to eliminate processor core hot spots.
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  36. Henry, G. Glenn; Parks, Terry; Martin-de-Nicolas, Arturo, Microprocessor including random number generator supporting operating system-independent multitasking operation.
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  38. Henry,G. Glenn; Parks,Terry, Microprocessor with instruction translator for translating an instruction for storing random data bytes.
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  43. Crispin,Thomas A.; Henry,G. Glenn; Parks,Terry, Microprocessor with selectivity available random number generator based on self-test result.
  44. Walker, Darryl G., Multi-chip non-volatile semiconductor memory package including heater and sensor elements.
  45. Walker, Darryl G., Multi-chip non-volatile semiconductor memory package including heater and sensor elements.
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  47. Walker, Darryl G., Multi-chip non-volatile semiconductor memory package including heater and sensor elements.
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  54. Walker, Darryl G., Power up of semiconductor device having a temperature circuit and method therefor.
  55. Lee,Hsin Chou; Chen,Wu Shin, Radio frequency temperature sensor and method of calibrating temperature therefor.
  56. Henry,G. Glenn; Parks,Terry, Random number generator bit string filter.
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  64. Walker, Darryl G., Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value.
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  66. Walker, Darryl G., Semiconductor device having variable parameter selection based on temperature.
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  76. Kirsch, Howard C., Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line.
  77. Kirsch, Howard C., Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals.
  78. Van De Graaff, Scott, Synchronous mirror delay with reduced delay line taps.
  79. Van De Graaff, Scott, Synchronous mirror delay with reduced delay line taps.
  80. Van De Graaff, Scott, Synchronous mirror delay with reduced delay line taps.
  81. Van De Graaff, Scott, Synchronous mirror delay with reduced delay line taps.
  82. Yang, Yizhang; Zhai, Jun, System and method for calibrating temperatures sensor for integrated circuits.
  83. Wen, Tianyu; Lin, Chris C.; Karr, Ronald S., System and method for performing online backup and restore of volume configuration information.
  84. Norman, Robert D; Schmidt, Dominik J., Systems and methods for self-calibration.
  85. Norman,Robert D; Schmidt,Dominik J., Systems and methods for self-calibration.
  86. Schmidt,Dominik J., Systems and methods for testing wireless devices.
  87. Lee, Kyong Ha, Temperature detecting apparatus.
  88. Walker, Darryl G., Temperature sensing circuit with hysteresis and time delay.
  89. Walker, Darryl G., Testing and setting performance parameters in a semiconductor device and method therefor.
  90. Walker, Darryl G., Testing and setting performance parameters in a semiconductor device and method therefor.
  91. Walker, Darryl G., Testing and setting performance parameters in a semiconductor device and method therefor.
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