초록 ▼

There is proposed a process for the monitoring of integrated circuits (ASICs 21, 22) in safety-critical applications, in which the ASICs (21, 22) with identical constructions are connected in parallel and simultaneously to all inputs. The ASICs (21, 22) operate closely synchronized with each other a

There is proposed a process for the monitoring of integrated circuits (ASICs 21, 22) in safety-critical applications, in which the ASICs (21, 22) with identical constructions are connected in parallel and simultaneously to all inputs. The ASICs (21, 22) operate closely synchronized with each other and mutually monitor each other. They carry out a comparison of interim results, end results and output data. The logic condition is monitored at different monitoring points; namely, the freely defineable interim and end results of an information processing, the suitable internal switching conditions and the internal signals at discrete scanning points in time.

대표청구항 ▼

[ What is claimed is:] [1.] A process for monitoring of application specific integrated circuits (ASICs), especially of application specific integrated circuits in safety-critical applications, characterized in that at least two application specific integrated circuits (ASICs 21, 22) of identical co

[ What is claimed is:] [1.] A process for monitoring of application specific integrated circuits (ASICs), especially of application specific integrated circuits in safety-critical applications, characterized in that at least two application specific integrated circuits (ASICs 21, 22) of identical construction are connected in parallel and simultaneously to all inputs, said at least two ASICs (21, 22) operate in close synchronism with each other, and wherein the two-channel structure which is formed from said at least two ASICs (21, 22) implements a comparison of interim results, end results and output data, and wherein the logic condition of said at least two ASICs (21, 22) is monitored at different monitoring points, and wherein each of the ASICs (21, 22) is provided with an input unit (31) for preprocessing and preparation of input data, a processing unit (32), an output unit (33) and a comparator unit (34), status storages (311, 312, 313; 321, 322, 323; 331, 332, 333) which are connected in series with tapped-off status information from the units (31, 32, 33, 34), wherein the input unit (31), the processing unit (32) and the output unit (33) are each respectively in an alternating relationship with a unit (35) for control and release of the comparison, and wherein the outputs and the inputs of each comparator unit (34) which is integrated in each of said ASICs (21, 22) are in a cross-over connection with each other, such that an input cell (341) of the first comparator unit (34) is connected with a status storage (343) of the second comparator unit (34), and conversely an input cell (341) of the second comparator unit (34) is connected with a status storage (343) of the first comparator unit (34), and a comparator (342) in each comparator unit (34) is presently switched to a circuit block (7) for monitoring of error recognition, watchdog and emergency switch-off.