초록 ▼

A stress relief substrate having a pair of ball grid arrays (BGAs) is interposed between a PC board and an electrical component. The BGAs are electrically connected through vias in the stress relief substrate to connect component circuitry to the PC board. In one embodiment, the BGAs are offset on a

A stress relief substrate having a pair of ball grid arrays (BGAs) is interposed between a PC board and an electrical component. The BGAs are electrically connected through vias in the stress relief substrate to connect component circuitry to the PC board. In one embodiment, the BGAs are offset on a flexible substrate so that there is some open space between the edges of electrically connected solder balls. This allows the substrate to warp during thermal cycling and absorb the stress caused by TCE mismatch. In another embodiment, the BGAs are aligned on a rigid substrate that is formed with holes interposed between the solder balls. This reduces the amount of material that interconnects the solder balls so that the substrate tends to flex rather than transfer the TCE stress to the solder balls.

대표청구항 ▼

[ I claim:] [1.] A ball grid array (BGA) mounted circuit, comprising:a printed circuit (PC) board;a board BGA mounted on said PC board and formed of first solder balls that are arranged in a first array pattern;a stress relief substrate having a top surface and having a bottom surface on said board

[ I claim:] [1.] A ball grid array (BGA) mounted circuit, comprising:a printed circuit (PC) board;a board BGA mounted on said PC board and formed of first solder balls that are arranged in a first array pattern;a stress relief substrate having a top surface and having a bottom surface on said board BGA;a component BGA on the top surface of said stress relief substrate and formed of second solder balls that are arranged in a second array pattern that is substantially identical to said first array pattern and that is laterally offset from said first array pattern, each of said second solder balls thus laterally offset from a corresponding one of said first solder balls and forming, with that first solder ball, one of a plurality of solder ball pairs;an array of electrical vias through said stress relief substrate with each of said vias positioned proximate to a respective one of said solder ball pairs;a plurality of first circuit traces positioned on the top surface of said stress relief substrate and each arranged to connect a respective one of said vias to the first solder ball of that via's respective solder ball pair;a plurality of second circuit traces positioned on the bottom surface of said stress relief substrate and each arranged to connect a respective one of said vias to the second solder ball of that via's respective solder ball pair; andan electrical component on said component BGA, said electrical component having a plurality of circuits that are connected to respective circuits on said PC board through said component BGA, said array of electrical vias and said board BGA;the first and second solder balls of each solder ball pair thus connected together and laterally offset from each other by a portion of said stress relief substrate that will flex during thermal cycling to absorb thermal coefficient of expansion (TCE) mismatch between said electrical component and said PC board.