$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/302
  • H01L-023/48
  • G03C-005/00
출원번호 US-0435434 (1999-11-22)
발명자 / 주소
  • Chooi Simon,SGX
  • Xu Yi,SGX
  • Zhou Mei Sheng,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 38  인용 특허 : 10

초록

A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by

대표청구항

[ What is claimed is:] [1.] A method of forming a damascene structure using a low dielectric constant passivation layer or etch stop layer, comprising the steps of:a. providing a semiconductor structure having a first conductive layer thereover;b. forming a passivation layer on said first conductive

이 특허에 인용된 특허 (10)

  1. Watts David ; Bajaj Rajeev ; Das Sanjit ; Farkas Janos ; Dang Chelsea ; Freeman Melissa ; Saravia Jaime A. ; Gomez Jason ; Cook Lance B., Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture.
  2. Farkas Janos ; Bajaj Rajeev ; Freeman Melissa ; Watts David K. ; Das Sanjit, Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers.
  3. Leedy Glenn J. (1061 E. Mountain Dr. Montecito CA 93108), Contact stepper printed lithography method.
  4. Nguyen Tue ; Peng Chien-Hsiung ; Ulrich Bruce Dale, Hard mask method for transferring a multi-level photoresist pattern.
  5. Stolmeijer Andre, Interconnect scheme for integrated circuits.
  6. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  7. Jain Ajay ; Lucas Kevin, Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC).
  8. Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.
  9. Brabazon Terry J. ; El-Kareh Badih ; Martin Stuart R. ; Rutten Matthew J. ; Kaanta Carter W., Precision analog metal-metal capacitor.
  10. Pramanick Shekhar, Semiconductor interconnect barrier for fluorinated dielectrics.

이 특허를 인용한 특허 (38)

  1. Woo, Christy Mei-Chu; Joo, Young-Chang; Lukanc, Todd, Barrier layer integrity test.
  2. Enicks, Darwin G., Boron etch-stop layer and methods related thereto.
  3. Grill, Alfred; Neumayer, Deborah A.; Rodbell, Kenneth P., Boron rich nitride cap for total ionizing dose mitigation in SOI devices.
  4. Grill, Alfred; Neumayer, Deborah A.; Rodbell, Kenneth P., Boron rich nitride cap for total ionizing dose mitigation in SOI devices.
  5. Nguyen, Son Van; Grill, Alfred; Haigh, Jr., Thomas J.; Mehta, Sanjay, C-rich carbon boron nitride dielectric films for use in electronic devices.
  6. Wright,Marilyn I.; Dakshina Murthy,Srikanteswara; Junker,Kurt H.; Patterson,Kyle, Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same.
  7. Calvin T. Gabriel ; Lynne A. Okada, Dielectric layer with treated top surface forming an etch stop layer and method of making the same.
  8. Chang,Hui Lin, Insulating layer having decreased dielectric constant and increased hardness.
  9. Enicks, Darwin G.; Chaffee, John Taylor; Carver, Damian A., Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto.
  10. Enicks, Darwin Gene; Chaffee, John; Carver, Damian A., Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto.
  11. Enicks,Darwin G., Integrated circuit structures having a boron-and carbon-doped etch-stop and methods, devices and systems related thereto.
  12. Cheng, Yana; Cao, Yong; Guggilla, Srinivas; Kesapragada, Sree Rangasai; Tang, Xianmin; Padhi, Deenesh, Interconnect structures and methods of formation.
  13. Sei Tsunoda JP; Hideharu Nobutoki JP; Noboru Mikami JP, LOW DIELECTRIC CONSTANT FILM COMPOSED OF BORON, NITROGEN, AND HYDROGEN HAVING THERMAL RESISTANCE, PROCESS FOR FORMING THE FILM, USE OF THE FILM BETWEEN SEMICONDUCTOR DEVICE LAYERS, AND THE DEVICE FOR.
  14. Broekaart, Marcel Eduard; Fortuin, Arnoud Willem, Metal etching method for an interconnect structure and metal interconnect structure obtained by such method.
  15. Kuei-Chun Hung TW; Vencent Chang TW; I-Hsiung Huang TW; Ya-Hui Chang TW, Method for forming via-first dual damascene interconnect structure.
  16. Enicks, Darwin G., Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator.
  17. Thomas, Danielle A.; Siegel, Harry Michael; Do Bento Vieira, Antonio A.; Chiu, Anthony M., Method for providing a redistribution metal layer in an integrated circuit.
  18. Chang, Ting-Chang; Liu, Po-Tsun; Mor, Yi-Shien, Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process.
  19. Naokatsu Ikegami JP, Method of dry etching organic SOG film.
  20. Hsieh, Chang Lin; Chen, Hui; Yuan, Jie; Ye, Yan, Method of etching carbon-containing silicon oxide films.
  21. Kinoshita, Takao; Orita, Kunihiko, Method of manufacturing a dual damascene structure using boron nitride as trench etching stop film.
  22. Hara, Kazusato; Funatsu, Keisuke; Imai, Toshinori; Noguchi, Junji; Ohashi, Naohumi, Method of manufacturing a semiconductor device and a semiconductor device.
  23. Kazusato Hara JP; Keisuke Funatsu JP; Toshinori Imai JP; Junji Noguchi JP; Naohumi Ohashi JP, Method of manufacturing a semiconductor device and a semiconductor device.
  24. Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG; Paul Kwok Keung Ho SG; Yi Xu SG; Simon Chooi SG; Yakub Aliyu SG, Method of manufacturing embedded organic stop layer for dual damascene patterning.
  25. Lee, Kwangduk Douglas; Rathi, Sudha; Sankarakrishnan, Ramprakash; Seamons, Martin Jay; Jamil, Irfan; Kim, Bok Hoen, Methods of dry stripping boron-carbon films.
  26. Chung-Shi Liu TW; Chen-Hua Yu TW, Passivation method for copper process.
  27. Kumada, Teruhiko; Nobutoki, Hideharu; Yasuda, Naoki, Plasma CVD apparatus, method for forming thin film and semiconductor device.
  28. Hsieh, Chang-Lin; Yuan, Jie; Chen, Hui; Panagopoulos, Theodoros; Ye, Yan, Process for selectively etching dielectric layers.
  29. Baek,Seoung Won, Semiconductor device having improved contact hole structure and method for fabricating the same.
  30. Umemoto, Takeshi, Semiconductor device with multi-layer interlayer dielectric film.
  31. Subramanian, Ramkumar; Lukanc, Todd P.; Wang, Fei, Slotted trench dual inlaid structure and method of forming thereof.
  32. Gibson, Jr., Gerald W; Jessen, Scott; Lytle, Steven Alan; Steiner, Kurt George; Vitkavage, Susan Clay, Split barrier layer including nitrogen-containing portion and oxygen-containing portion.
  33. Thomas, Danielle A.; Siegel, Harry Michael; Do Bento Vieira, Antonio A.; Chiu, Anthony M., System for providing a redistribution metal layer in an integrated circuit.
  34. Cotte, John Michael; Hoivik, Nils Deneke; Jahnes, Christopher Vincent; Wisnieff, Robert Luke, Ta-TaN selective removal process for integrated device fabrication.
  35. Cotte,John Michael; Hoivik,Nils Deneke; Jahnes,Christopher Vincent; Wisnieff,Robert Luke, Ta-TaN selective removal process for integrated device fabrication.
  36. Cotte, John M.; Hoivik, Nils; Jahnes, Christopher V.; Wisnieff, Robert L., Ta—TaN selective removal process for integrated device fabrication.
  37. Calvin T. Gabriel ; Lynne A. Okada, Ultra thin etch stop layer for damascene process.
  38. Licheng M. Han SG; Yi Xu SG; Joseph Zhifeng Xie SG; Mei Sheng Zhou SG; Simon Chooi SG, Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로