초록 ▼

A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second s

A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure.

대표청구항 ▼

[ What is claimed is:] [1.] A method of manufacturing a salicide layer suitable for formation on a substrate having a memory region and a logic circuit region, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second g

[ What is claimed is:] [1.] A method of manufacturing a salicide layer suitable for formation on a substrate having a memory region and a logic circuit region, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region, the method comprising the steps of:forming a protective layer over the memory region;forming a first salicide layer on the second gate structure and the second source/drain region in the logic circuit region after forming the protective layer over the memory region, whereby the first gate structure and the first source/drain region remain free from the first salicide layer;removing the protective layer to expose the first gate structure and the first source/drain region after forming the first salicide layer;forming a dielectric layer over the substrate;removing a portion of the dielectric layer to expose the first gate structure and the first salicide layer above the second gate structure; andforming a second salicide layer on the first gate structure and the second gate structure.