초록 ▼

A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically recon

A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA). The IFU directs reconfiguration operations, instruction fetch and decode operations, memory access operations, and issues control signals to the DOU and the AOU to facilitate instruction execution. The DOU performs data computations, and the AOU performs address computations. Each T-machine is a data transfer device having a common interface and control unit, one or more interconnect I/O units, and a second local time-base unit. The GPIM is a scalable interconnect network that facilitates parallel communication between T-machines. The set of T-machines and the GPIM facilitate parallel communication between S-machines.

대표청구항 ▼

[ What is claimed is:] [1.] A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a

[ What is claimed is:] [1.] A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first instruction set architecture (ISA) that executes instructions from a first instruction set and a second instruction set architecture (ISA) that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first ISA being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second ISA, wherein each ISA for the changeable internal hardware organization is capable of being represented as binary data in a memory device, and wherein the reconfigure directive is one of the instructions in the first instruction set.