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[미국특허] Semiconductor die back side surface and method of fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0481947 (2000-01-12)
발명자 / 주소
  • Jiang Tongbi
  • Cobbley Chad A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Trask Brett
인용정보 피인용 횟수 : 68  인용 특허 : 25

초록

A method of physically altering the backside surface of a semiconductor wafer or other substrate, and resulting article, to improve adhesion between the backside surface of semiconductor dice singulated from the wafer and a die attach adhesive or encapsulation compound. The physically altered backsi

대표청구항

[ What is claimed is:] [1.] A semiconductor component assembly, comprising:a semiconductor component comprising an active surface and a back side surface, said back side surface having a substantially non-planar texture wherein said substantially non-planar texture of the back side surface has a pea

이 특허에 인용된 특허 (25) 인용/피인용 타임라인 분석

  1. King Jerrold L. (Boise ID) Brooks J. Mike (Caldwell ID) Moden Walter L. (Boise ID), Adhesion enhanced semiconductor die for mold compound packaging.
  2. Ebe Kazuyoshi (Saitama JPX) Narita Hiroaki (Saitama JPX) Taguchi Katsuhisa (Saitama JPX) Akeda Yoshitaka (Saitama JPX) Saito Takanori (Saitama JPX), Adhesive sheets.
  3. Tsutsumi Yukio (Tokyo JPX) Kumabe Shigeo (Tokyo JPX) Takahashi Keisuke (Tokyo JPX), Apparatus for polishing wafer.
  4. Lund Douglas E. (13304 Purple Sage Dallas TX 75240), Automatic chemical and mechanical polishing system for semiconductor wafers.
  5. La Tho Le ; Venkatkrishnan Subramanian ; Ramsbey Mark T. ; Thomas Jack F. ; Early Kathleen, Backside wafer polishing for improved photolithography.
  6. Lim Thiam B. (Pasir Ris Gardens SGX) Saitoh Tadashi (Mandarin Garden SGX) Seow Boon Q. (Greenridge Crescent SGX), Integrated circuit device having a polyimide moisture barrier coating.
  7. Ebihara Kazumi,JPX, Leadframe and resin-sealed semiconductor device.
  8. Robbins John (Sherman TX) Boston Ricky L. (Denison TX), Method and apparatus for back side damage of silicon wafers.
  9. Ball Michael B., Method and apparatus for grinding wafers.
  10. Ganesan Sankaranarayanan (Chandler AZ) Berg Howard M. (Scottsdale AZ), Method and apparatus for improving interfacial adhesion between a polymer and a metal.
  11. Leach Michael A., Method and structure for polishing a wafer during manufacture of integrated circuits.
  12. Tu Tuby,TWX ; Chen Kuang-Chao,TWX, Method for forming trenched polysilicon structure.
  13. Berg Howard M. ; Ganesan Sankaranarayanan ; Lewis Gary L. ; Hawkins George W. ; Sloan James W. ; Bolton Scott C., Method for making a moisture resistant semiconductor device having an organic substrate.
  14. Tsuji Kazuto,JPX ; Yoneda Yoshiyuki,JPX ; Orimo Seiichi,JPX ; Nomoto Ryuji,JPX ; Onodera Masanori,JPX ; Sakoda Hideharu,JPX, Method for producing a semiconductor device.
  15. Lawrence John E. (Cupertino CA), Method for reclaiming substrate from semiconductor wafers.
  16. Takemura Kazumi (Tokyo JPX) Toyokawa Fumitoshi (Tokyo JPX) Mikami Masao (Tokyo JPX), Method of gettering semiconductor wafers with an excimer laser beam.
  17. Nakanishi Toshiro (Kawasaki JPX) Sato Yasuhisa (Kawasaki JPX), Method of making a semiconductor memory device having a floating gate.
  18. Tonti William R. ; Mandelman Jack A. ; Zalesinski Jerzy M. ; Furukawa Toshiharu ; Nguyen Son V. ; Chidambarrao Dureseti, Method of manufacturing an integrated ULSI heatsink.
  19. Earl Michael R. (Kokomo IN) Detterich Russell A. (Kokomo IN) Yancey Robert A. (Carmel IN), No coat backside wafer grinding process.
  20. Billett Bruce H., Polishing pad conditioning surface having integral conditioning points.
  21. Buchner Alfred (Pischelsdorf ATX) Kuhn-Kuhnenfeld Franz (Emmerting DEX) Auer Walter (Burghausen DEX), Process for the backside-gettering surface treatment of semiconductor wafers.
  22. Okabe Yoshifumi (Nagoya JPX) Yamaoka Masami (Anjo JPX) Kuroyanagi Akira (Okazaki JPX), Semiconductor device and method of manufacturing same.
  23. Yamada Shigeru,JPX ; Uchida Yasufumi,JPX ; Murakami Noriko,JPX ; Shizuno Yoshinori,JPX, Semiconductor device having a die pad structure for preventing cracks in a molding resin.
  24. Lowrey Tyler A. (Boise ID) Doan Trung T. (Boise ID) Sandhu Gurtej S. (Boise ID), Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion.
  25. Bennett Richard E. ; Bird Gerald C. ; Nestegard Mark K. ; Rudin Eleanor, Semiconductor wafer processing adhesives and tapes.

이 특허를 인용한 특허 (68) 인용/피인용 타임라인 분석

  1. Monthei, Dean L.; Espinoza, Antonio; Holgado, Waldemar J., Apparatus and method for reduced delamination of an integrated circuit module.
  2. Park, Sang Wook, Chip size stack package and method of fabricating the same.
  3. Park, Sang Wook, Chip size stack package and method of fabricating the same.
  4. Obu, Isao; Umemoto, Yasunari; Shibata, Masahiro, Compound semiconductor substrate and power amplifier module.
  5. Hara,Kazumi, Dicing sheet, manufacturing method thereof, and manufacturing method of semiconductor apparatus.
  6. Hagen,Robert Christian; Jerebic,Simon, Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same.
  7. Yamanaka, Takahiro, Electronic device and actuator using the same.
  8. Ding, Xiaoyi; Nowicki, James, Embedded structures for high glass strength and robust packaging.
  9. Ding, Xiaoyi; Nowicki, James, Embedded structures for high glass strength and robust packaging.
  10. Xu, Shuming; Zheng, Yi, Enhanced thermal transfer in a semiconductor structure.
  11. Chiu, Chin-Tien; Bhagath, Shrikar; Zhang, Yuang; Zhong, Lu; Qian, Kaiyou, Extrinsic gettering on semiconductor devices.
  12. Huang, Wen-Home; Tseng, Wen-Tsung; Lin, Chang-Fu; Tsai, Ho-Yi; Hsiao, Cheng-Hsu, Fabrication method of semiconductor package.
  13. Su,Michael Zhuoying; Eppes,David Harry, Integrated circuit with increased heat transfer.
  14. Goida, Thomas M.; Xue, Xiaojie, Integrated device die and package with stress reduction features.
  15. Goida, Thomas M.; Xue, Xiaojie, Integrated device die and package with stress reduction features.
  16. Xu, Shuming, Integrated on-chip junction capacitor for power management integrated circuit device.
  17. Juengling, Werner, Method and apparatus for designing a pattern on a semiconductor surface.
  18. Juengling,Werner, Method and apparatus for designing a pattern on a semiconductor surface.
  19. Lee, SungYoon; Shin, JungHoon; Yoon, BoHan, Method for directional grinding on backside of a semiconductor wafer.
  20. Kim,Hang Ja; Jung,Eun Kyoung, Method of forming TEM specimen and related protection layer.
  21. Meyers,John G., Method of forming a multi-die semiconductor package.
  22. Sunohara,Masahiro; Murayama,Kei; Higashi,Mitsutoshi, Method of production of multilayer circuit board with built-in semiconductor chip.
  23. Wachtler, Kurt P., Method of separating semiconductor dies from a wafer.
  24. Rinne, Glenn A.; Engel, Kevin; Roe, Julia; Berry, Chirstopher John, Methods of forming back side layers for thinned wafers.
  25. Jiang, Tongbi, Methods of thinning microelectronic workpieces.
  26. Jiang, Tongbi; Luo, Shijian, Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers.
  27. Sri Jayantha,Sri M.; Hougham,Gareth; Kang,Sung; Mok,Lawrence; Dang,Hien; Sharma,Arun, Microelectronic devices and methods.
  28. Meyers, John G., Multi-die semiconductor package.
  29. Jiang, Tongbi; Connell, Mike; Li, Li; Hollingshead, Curtis, Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate.
  30. Thurgood, Blaine; Corisis, David, Packaged microelectronic devices and methods for packaging microelectronic devices.
  31. Viswanathan, Lakshminarayan; Mahalingam, L. M.; Abdo, David F.; Molla, Jaynal A., Packaged semiconductor devices and methods of their fabrication.
  32. Juengling, Werner, Pattern generation on a semiconductor surface.
  33. Juengling,Werner, Pattern generation on a semiconductor surface.
  34. Derderian,James M.; Draney,Nathan R., Process for strengthening semiconductor substrates following thinning.
  35. Chao,Iwen; Eskildsen,Steve R., Semiconducting device with folded interposer.
  36. Chao,Iwen; Eskildsen,Steve R., Semiconducting device with folded interposer.
  37. Chao,Iwen; Eskildsen,Steve R., Semiconducting device with folded interposer.
  38. Sahaida,Scott R.; Chao,Iwen, Semiconducting device with stacked dice.
  39. Pagaila, Reza Argenty, Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation.
  40. Hiroshi Haji JP; Shoji Sakemi JP, Semiconductor device and method of manufacturing the same.
  41. Yoneyama, Rei; Okabe, Hiroyuki; Nishida, Nobuya; Obara, Taichi, Semiconductor device and semiconductor module.
  42. Sumikawa, Masato; Tanaka, Kazumi, Semiconductor device having reinforcement member and method of manufacturing the same.
  43. Viswanathan, Lakshminarayan; Mahalingam, L. M.; Abdo, David F.; Molla, Jaynal A., Semiconductor device with mechanical lock features between a semiconductor die and a substrate.
  44. Haji, Hiroshi; Sakemi, Shoji, Semiconductor device with reinforcing resin layer.
  45. Sakai, Tadahiko; Ozono, Mitsuru; Maeda, Tadashi, Semiconductor device, method of manufacturing the device and method of mounting the device.
  46. Wachtler, Kurt P., Semiconductor die with contoured bottom surface and method for making same.
  47. Shivkumar, Bharat; Cheah, Chuan, Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance.
  48. Huang, Wen-Home; Tseng, Wen-Tsung; Lin, Chang-Fu; Tsai, Ho-Yi; Hsiao, Cheng-Hsu, Semiconductor package and fabrication method thereof.
  49. Newman, Robert A.; Weidler, Jaime D., Semiconductor packaging apparatus for controlling die attach fillet height to reduce die shear stress.
  50. Derderian,James M.; Draney,Nathan R., Semiconductor substrate.
  51. Kirby,Kyle K., Semiconductor wafers including one or more reinforcement structures and methods of forming the same.
  52. Cobbley, Chad A.; Jackson, Timothy L., Stacked die module and techniques for forming a stacked die module.
  53. Cobbley,Chad A.; Jackson,Timothy L., Stacked die module and techniques for forming a stacked die module.
  54. Cobbley,Chad A.; Jackson,Timothy L., Stacked die module and techniques for forming a stacked die module.
  55. Cobbley,Chad A.; Jackson,Timothy L., Stacked die module and techniques for forming a stacked die module.
  56. Cobbley, Chad A.; Jackson, Timothy L., Stacked die module including multiple adhesives that cure at different temperatures.
  57. Draney,Nathan R.; Derderian,James M., Substrate thinning including planarization.
  58. Draney,Nathan R.; Derderian,James M., Substrate with enhanced properties for planarization.
  59. Hsu, Shih Ping, Surface roughening method for embedded semiconductor chip structure.
  60. Lee, SungYoon; Shin, JungHoon; Yoon, BoHan, System and method for directional grinding on backside of a semiconductor wafer.
  61. Viswanathan, Lakshminarayan; Molla, Jaynal A., Thick-silver layer interface for a semiconductor die and corresponding thermal layer.
  62. Ding, Xiaoyi; Frye, Jeffrey James, Thin semiconductor die package.
  63. Derderian, James M.; Draney, Nathan R., Thinned, strengthened semiconductor substrates and packages including same.
  64. Lee,Myoung Rack; Kim,Jung Sun, Transmission electron microscope specimen and method of manufacturing the same.
  65. Jiang,Tongbi; Connell,Mike; Li,Li; Hollingshead,Curtis, Treatment of a ground semiconductor die to improve adhesive bonding to a substrate.
  66. Dydyk, Mark; Urquiza, Arturo; Singleton, Charles; McIntosh, Tim, Wafer backside grinding with stress relief.
  67. Kirby,Kyle K., Wafer reinforcement structure and methods of fabrication.
  68. Rinne, Glenn A.; Engel, Kevin; Roe, Julia; Berry, Christopher John, Wafers including patterned back side layers thereon.

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