초록 ▼

The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the I

The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

대표청구항 ▼

[ claims having thus described our invention, what we claim as new, and desire to secure Letters Patent is:] [1.] A method for forming an aluminum (Al) contact in electrical communication with copper (Cu) wiring comprising:(a) forming a passivating layer on an integrated circuit (IC) semiconductor w

[ claims having thus described our invention, what we claim as new, and desire to secure Letters Patent is:] [1.] A method for forming an aluminum (Al) contact in electrical communication with copper (Cu) wiring comprising:(a) forming a passivating layer on an integrated circuit (IC) semiconductor wafer containing Cu wiring embedded therein;(b) forming terminal via openings through said passivating layer to expose said Cu wiring;(c) forming a barrier layer at least over said exposed Cu wiring, on the side walls of said terminal via openings and on regions of said barrier layer near said terminal via openings;(d) forming an Al stack on said barrier layer at least in said terminal via openings and on regions of the barrier layer near said terminal via openings;(e) patterning and etching said Al stack and said barrier layer;(f) forming a second passivating layer over said patterned Al stack; and(g) providing second openings in said second passivating layer so as to expose regions of said patterned Al stack located on top of said Cu wiring whereby said Cu wiring is protected from environmental exposure or attack by etching chemistries and from the problem of Cu--Al intermixing.