초록 ▼

A master-slave flip-flop and method is provided for use with critical path circuits, for example, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input i

A master-slave flip-flop and method is provided for use with critical path circuits, for example, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input inverter coupled to the pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter. The output of the driving inverter is coupled to the slave stage which includes a second pass gate through which the output of the driving inverter is applied to the master-slave flip-flop output. The above architecture results in a fast setup time and a fast clock-to-Q time without the problems associated with kickback. Also, the output of the master-slave flip-flop is tristatable.

대표청구항 ▼

[ Therefore, having thus described the invention, at least the following is claimed:] [1.] A logical circuit comprising;at least two master-slave flip-flops, each of the master-slave flip-flops having an output coupled to a common output bus;each of the master-slave flip-flops comprising:a master st

[ Therefore, having thus described the invention, at least the following is claimed:] [1.] A logical circuit comprising;at least two master-slave flip-flops, each of the master-slave flip-flops having an output coupled to a common output bus;each of the master-slave flip-flops comprising:a master stage having a first pass gate, an input inverter coupled to the first pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter, the driving inverter being larger than the input inverter such that a slew rate of a voltage output of the driving inverter exceeds a slew rate of a voltage output of the input inverter; anda slave stage coupled to the output of the driving inverter, the slave stage having a second pass gate coupled to the output of the driving inverter, and, a feedback amplifier coupled to the output of the second pass gate; andwherein the driving inverter of each master-slave flip-flop is driving the common output bus such that a first one of the master-slave flip-flops is enabled to drive the common output bus provided respective clock signals of all of the other master-slave flip-flops are off.