초록

This invention relates generally to Fibre Channel Loop topology in a computer system and more particularly to structure and method for by-passing a failed controller connected in a dual-active mode Fibre Channel Loop.

대표청구항 ▼

[ I claim:] [1.] A device bypass circuit for a fibre channel communications loop, said circuit comprising:a first clock recovery circuit coupled to a first input port for receiving a first device signal from a first device and for generating a first regenerated device signal;a second clock recovery

[ I claim:] [1.] A device bypass circuit for a fibre channel communications loop, said circuit comprising:a first clock recovery circuit coupled to a first input port for receiving a first device signal from a first device and for generating a first regenerated device signal;a second clock recovery circuit coupled to a second input port for receiving a first controller signal from a first controller and for generating a first regenerated controller signal;a signal detection unit for detecting a valid first device signal and for generating a selector signal having a first state when a valid first device signal is detected and a second state when no valid first device signal is detected; anda switchable selector circuit receiving said first regenerated device signal, said first regenerated controller signal, and said first selector signal; said switchable selector circuit selectively passing one of said first regenerated device signal or said first regenerated controller signal in response to said first or second state of said first selector signal.