초록 ▼

In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within

In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

대표청구항 ▼

[What is claimed is:] [1.]providing a semiconductor substrate;forming a tungsten plug overlying the semiconductor substrate;forming a dielectric layer overlying the tungsten plug;removing a portion of the dielectric layer to expose at least a portion of the tungsten plug within an opening;forming a

[What is claimed is:] [1.]providing a semiconductor substrate;forming a tungsten plug overlying the semiconductor substrate;forming a dielectric layer overlying the tungsten plug;removing a portion of the dielectric layer to expose at least a portion of the tungsten plug within an opening;forming a catalytic layer comprising a palladium-tin alloy within the opening;forming a conductive seed layer within the opening and overlying the catalytic layer, wherein the conductive seed layer is formed using an electroless plating process; andforming a conductive metal layer overlying the conductive seed layer, wherein the conductive metal layer is formed using an electroplating process.