초록 ▼

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

대표청구항 ▼

[What is claimed is:] [1.]a master latch receiving an input of the flip-flop;a logic gate coupled to receive an output of the master latch; anda slave latch coupled to the master latch and to an output of the logic gate, wherein the master latch, the logic gate, and the slave latch are each responsi

[What is claimed is:] [1.]a master latch receiving an input of the flip-flop;a logic gate coupled to receive an output of the master latch; anda slave latch coupled to the master latch and to an output of the logic gate, wherein the master latch, the logic gate, and the slave latch are each responsive to a clock signal, wherein the master latch and the logic gate each include a plurality of transistor branches, each for coupling a corresponding node to a first power supply node or a second power supply node, and wherein the control input for setting or resetting the flip-flop is not input to any transistor branch of the master latch or the logic gate that is responsive to an active edge of the clock signal.