초록 ▼

A semiconductor memory device and a fabricating method therefor are disclosed. The semiconductor memory device includes a peripheral region and a core region containing a transistor with at least a p+ impurity region. An inter-layer insulating layer is formed on an entire surface of a semiconductor

A semiconductor memory device and a fabricating method therefor are disclosed. The semiconductor memory device includes a peripheral region and a core region containing a transistor with at least a p+ impurity region. An inter-layer insulating layer is formed on an entire surface of a semiconductor substrate. Then the insulating layer is etched by using a contact forming mask until the surface of the p+ impurity region of the core region is exposed, so as to form contact holes. The contact holes are then filled with a metal to form contacts so as to be electrically connected to the semiconductor substrate. The present invention solves the conventional problem that the contact plug reacts with the impurity ions of the p+ impurity region during the heat treatment, thereby increasing the contact resistance. That is, in the present invention, the contact for the wiring on the semiconductor substrate of the p+ impurity region is directly formed after the formation of the memory cells in the cell region at a high temperature. Therefore, the succeeding high temperature process steps are simplified, and therefore, the metal layer is prevented from being reacted with the impurity ions, thereby preventing the increase of the contact resistance. Thus, a stable performance of the semiconductor device is ensured.

대표청구항 ▼

[What is claimed is:] [1.]forming a gate electrode on a semiconductor substrate, and covering an upper surface and side walls of said gate electrode with an insulating material;implanting impurity ions into said semiconductor substrate at both sides of said gate electrode to form a first conduction

[What is claimed is:] [1.]forming a gate electrode on a semiconductor substrate, and covering an upper surface and side walls of said gate electrode with an insulating material;implanting impurity ions into said semiconductor substrate at both sides of said gate electrode to form a first conduction type region and a second conduction type region;forming a first insulating layer on said semiconductor substrate, covering said gate electrode;etching said first insulating layer until a surface of said gate electrode and a surface of said semiconductor substrate of said first conduction type region are exposed, so as to form contact holes;filling said contact holes with a metal layer to form contact plugs;forming a pad on said first insulating layer so as to be electrically connected to said contact plugs, and making an upper face and side walls of said pad covered with the insulating material;forming a second insulating layer on said first insulating layer, covering said pad;sequentially etching said second and first insulating layers and said insulating material until a surface of said semiconductor substrate of at least said second conduction type region and a surface of said pad are exposed, so as to form second contact holes; andfilling said second contact holes with a metal layer to form contacts for connecting a wiring.