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Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0564682 (2000-05-04)
우선권정보 JP0127120 (1999-05-07)
발명자 / 주소
  • Ito Daisuke,JPX
  • Kitahara Yuichi,JPX
출원인 / 주소
  • Shinko Electric Industries Co., Ltd., JPX
대리인 / 주소
    Pennie & Edmonds LLP
인용정보 피인용 횟수 : 57  인용 특허 : 3

초록

A semiconductor device comprising an insulation film covering a semiconductor chip so as to expose electrodes or pads fabricated in the chip and wiring lines located on the insulation film and connected to the respective electrodes or pads is produced by a method which comprises: providing a semicon

대표청구항

[What is claimed is:] [1.]providing a semiconductor chip provided with an insulation film covering the chip so as to expose a conductor layer for electrodes or pads fabricated in the chip,ion milling the surface of the chip provided with the insulation film by a mixed gas of argon and hydrogen,formi

이 특허에 인용된 특허 (3)

  1. Suguro Kyoichi (Yokohama JPX) Okano Haruo (Tokyo JPX), Method of manufacturing a multilayered metallization structure in which the conductive layer and insulating layer are se.
  2. Suguro Kyoichi (Yokohama JPX) Okano Haruo (Tokyo JPX), Method of manufacturing semiconductor device.
  3. Suguro Kyoichi (Yokohama JPX) Okano Haruo (Tokyo JPX), Method of manufacturing semiconductor device.

이 특허를 인용한 특허 (57)

  1. Cowens,Marvin W.; Murtuza,Masood; Yamunan,Vinu; Odegard,Charles; Coffman,Phillip R., Adhesion by plasma conditioning of semiconductor chip.
  2. Cowens,Marvin W.; Murtuza,Masood; Yamunan,Vinu; Odegard,Charles; Coffman,Phillip R., Adhesion by plasma conditioning of semiconductor chip.
  3. Cowens, Marvin W.; Murtuza, Masood; Yamunan, Vinu; Odegard, Charles; Coffman, Phillip R., Adhesion by plasma conditioning of semiconductor chip surfaces.
  4. Cowens,Marvin W.; Murtuza,Masood; Yamunan,Vinu; Odegard,Charles; Coffman,Phillip R., Adhesion by plasma conditioning of semiconductor chip surfaces.
  5. Cowens,Marvin W.; Murtuza,Masood; Yamunan,Vinu; Odegard,Charles; Coffman,Phillip R., Adhesion by plasma conditioning of semiconductor chip surfaces.
  6. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Circuitry component and method for forming the same.
  7. Crawford, Edward J., FIB/RIE method for in-line circuit modification of microelectronic chips containing organic dielectric.
  8. Crawford, Edward J., FIB/RIE method for in-line circuit modification of microelectronic chips containing organic dielectric.
  9. Nakanishi, Hiroyuki; Ishio, Toshiya; Mori, Katsunobu, Integrated semiconductor circuit including electronic component connected between different component connection portions.
  10. Wang Ying-Lang,TWX ; Tsan Chun-Ching,TWX ; Dun Jowei,TWX ; Chien Hung-Ju,TWX, Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry.
  11. Umemoto,Mitsuo; Hoshino,Masataka; Terao,Hiroshi, Manufacturing method of semiconductor device.
  12. Nagata,Kazunari, Manufacturing process of semiconductor device.
  13. Yu, Hsiu-Mei; Chou, Ken-Shen; Hsu, Shun-Liang, Method and apparatus for polymer dielectric surface recovery by ion implantation.
  14. Ito,Daisuke, Method of forming conductor wiring pattern.
  15. Yamasaki, Yasuo; Kato, Hiroki, Method of manufacturing a semiconductor device.
  16. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  23. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  24. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  25. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  26. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  27. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  28. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  30. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  31. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  32. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  33. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  34. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  35. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  36. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  37. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  38. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  39. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  41. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  42. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  43. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  44. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Post passivation structure for a semiconductor device and packaging process for same.
  45. Katagiri, Mitsuaki; Shirai, Yuji; Kado, Yoshiyuki, Semiconductor device and a method of manufacturing the same.
  46. Strothmann, Thomas J.; Yoon, Seung Wook; Lin, Yaojian, Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP).
  47. Zhang, Zhen; Kuechenmeister, Frank; Bravo, Jaime; Su, Michael; Gannamani, Ranjit; Lim, Kevin, Semiconductor device having a filled trench structure and methods for fabricating the same.
  48. Anzai, Noritaka, Semiconductor device with signal line having decreased characteristic impedance.
  49. Anzai,Noritaka, Semiconductor device with signal line having decreased characteristic impedance.
  50. Anzai,Noritaka, Semiconductor device with signal line having decreased characteristic impedance.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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